psp 2.0 error in nand llc driver?

Can anybody reply me?

When I use DA830 SYS/BIOS PSP ver 2.10.01 I have a timing problems with NAND.

To my mind the reason is unproper configuration of the EMIFA in the llc_nand.c

Yuriy

Yuriy,

Are you using the sample application provided in the PSP? If not, then could you please provide us your custom configuration ?

You have mentioned that you are facing the timing issue, are you abservinng any data corruption or anything like this?

Could you please explain, the place at which you are observing the issue? Eg: read or write, command mode or data transaction mode etc

Thanks and Regards,

Sandeep K

Sandeep,

Just tell me, is it OK:

#define LLC_NAND_MEMORY_MAPPED_AT     (CSL_EMIFA_CS3_ADDR)

...........................................................................................................

Ptr LLC_nandInit(LLC_nandInitConfig  const *initCfg,
                 PSP_nandDeviceInfo       **devInfo)
{
...........................................................................................................
        hNandObj->regs->NANDFCR = CSL_EMIFA_NANDFCR_RESETVAL;

        switch (initCfg->instanceId)
        {
            /* For instance ID 0, the following are the NAND addresses        */
            case 0:  /* CS3 */
                hNandObj->CExDATA = (UInt32)LLC_NAND_MEMORY_MAPPED_AT;

...........................................................................................................

}

static Void LLC_nandSetWaitTime(LLC_nandObj           *hNandObj,
                                PSP_nandDeviceTiming  *devTiming)
{
...........................................................................................................
        /* Write the device wait timing based on the instance selected        */
        switch (hNandObj->instanceId)
        {
            /* Configure the wait timing for chip select 2                    */
            case 0:
                hNandObj->regs->CE4CFG &= CSL_EMIFA_CE4CFG_ASIZE_MASK;
                hNandObj->regs->CE4CFG |= timing;
                break;

            default:
                break;
        }
    }while (0);
}

static Void LLC_nandSetDataWidth(LLC_nandObj *hNandObj, UInt8 dataWidth)
{
    /* Validate the input parameters */
    Assert_isTrue((NULL != hNandObj), Nand_A_badParameter);

    hNandObj->regs->CE4CFG &= 0xFFFFFFFC;
    hNandObj->regs->CE4CFG |= dataWidth;

}

Yuriy

Yuriy,

The source code that you have provided is seems to be Ok.

Could you please answer some of the questions below,

    1. Are you using the sample application provided in the PSP? If not, then could you please provide us your custom configuration ?

    2. Are you using the using the driver in raw mode or through file system?

    2. You have mentioned that you are facing the timing issue, are you abservinng any data corruption or anything like this?

    3. Could you please explain, the place at which you are observing the issue? Eg: read or write, command mode or data transaction mode etc

    4. Are you using custom board with the same NAND device?

These informations are required to analyse the problem and provide the possible solution. 

Thanks and Regards,

Sandeep k

Sandeep,

please, look at the code of the NAND LLC driver attentively.

From soc_DA830.h

/** @brief Base address of EMIFA_CS3 memory                                   */
#define CSL_EMIFA_CS3_ADDR                  (0x62000000u)

i.e. NAND is mapped to the CS3 address space if the EMIFA

From cslr_emifa2.h

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 REVID;
    volatile Uint32 AWCC;
    volatile Uint32 SDCR;
    volatile Uint32 SDRCR;
    volatile Uint32 CE2CFG;
    volatile Uint32 CE3CFG;
    volatile Uint32 CE4CFG;
    volatile Uint32 CE5CFG;
...........................................................
} CSL_EmifaRegs;

i.e. CE4CFG has 24 byte offset from base address of the register file (#define CSL_EMIFA_0_REGS (0x68000000u) in soc_DA830.h)

CE4CFG has address 0x68000018u

It`s an asynchronous configuration register for the CS4 address space of the EMIFA

So, the driver sets timing for the CS4 address space and then works with the CS3 address space of the EMIFA !

Am I wrong?

Best regards,

Yuriy

Yuriy,

As mentioned in the previous post, I have raised an IR (defect tracking mechanism) and its reference number is "SDOCM00078730 ".

Thanks and Regards,

Sandeep K