AM3352: DDR tRPST DQS diff test

Daniel Cheng1

Mastermind 7145 points

Part Number: AM3352

Hi Expert,

I suppose that DDR tRPST DQS diff test will stop on 0 V such as Orange frame on pic.1

pic1.

But the tail signal is not stop on 0 V in in actuality such as pic2

pic2

Check the signal by DQS diff

DQS(+) will not return to -VTT such as pic3 when Read.

pic.3: DQS diff. Read

But Write signal is correct such as pic.4

pic.4 DQS diff. Write

Is the behavior correct or AM3352 setting issue??

Will the behavior cause any risk?

Thanks

Daniel

over 5 years ago

0 JJD over 5 years ago

TI__Guru* 86600 points

Daniel, the portion you outlined in orange is not during an active read or write, so it is really up to the load on the signal or how the signal is terminated. Note that during a read, the DDR is driving the DQS signal. Ultimately, i don't think the behavior will be an issue

Regards,

James

0 Daniel Cheng1 over 5 years ago in reply to JJD

Mastermind 7145 points

Hi James

According JEDEC standard DQS Diff.，the terminated signal should be 0 V, Is it ok that AM3352 does not follow this standard?Is it processor limitation?

Thanks

Daniel

0 Daniel Cheng1 over 5 years ago in reply to Daniel Cheng1

Mastermind 7145 points

Hi James

There is no update since 7/10.

Is there any good news?

Daniel

0 JJD over 5 years ago in reply to Daniel Cheng1

TI__Guru* 86600 points

Daniel, if you are concerned, you can try enabling a weak pulldown on DQS and pullup on DQSn by changing ddr_data0_ioctrl and ddr_data1_ioctrl from 0x18B to 0x2000018B

Regards,

James

0 Daniel Cheng1 over 5 years ago in reply to JJD

Mastermind 7145 points

Hi James

changing ddr_data0_ioctrl and ddr_data1_ioctrl from 0x18B to 0x2000018B

Enable weak pulldown, but the test result is same.

The signal is not stop on 0 V

Do I have to change the other settings?

Thanks

Daniel

0 Daniel Cheng1 over 5 years ago in reply to Daniel Cheng1

Mastermind 7145 points

Hi James

Is there any update?

Thanks

Daniel

0 JJD over 5 years ago in reply to Daniel Cheng1

TI__Guru* 86600 points

Daniel, can you dump the value of the SDRAM_CONFIG register?

Regards,

James

0 Daniel Cheng1 over 5 years ago in reply to JJD

Mastermind 7145 points

Hi James

#define ALLOPP_DDR3_SDRAM_CONFIG 0x63C25B32

Thanks for your help.

Daniel

0 JJD over 5 years ago in reply to Daniel Cheng1

TI__Guru* 86600 points

Daniel, did you use the AM335x EMIF tool https://www.ti.com/lit/pdf/sprack4 to configure the registers? Can you send the spreadsheet associated with your configuration, along with the DDR part number?

In SDRAM Config register, you have different termination set in the dynamic ODT vs normal ODT. Is there a reason for this?

Regards,

James

Processors

Processors forum

AM3352: DDR tRPST DQS diff test