Hello,
In the spru590 (TMS320VC5510 DSP external memory interface (EMIF) reference guide) of august 2004 one says (page 40 - section 2-10) :
The EMIF checks ARDY on the third rising edge of the CPU clock before the
end of the programmed strobe period. If ARDY is detected low at that time, the
strobe period is extended by 1 CPU clock cycle. For each subsequent CPU
clock rising edge that ARDY is sampled low, the strobe period is extended by
1 CPU clock cycle.
My question is :
What if ARDY is high on the third rising edge of the CPU clock before the end of the programmed strobe period and only goes low on the second or the first rising edge of the CPU clock before the end of the programmed strobe periode ?
Differently formulated my question would be :
Is "ARDY high on the third rising edge of the CPU clock before the end of the programmed strobe period" a necessary condition for inserting extra cycles ?
Best regards,
Jerome.
