AM5728: PCIe write into Mailbox module

Sean DeHarde

Part Number: AM5728

In an attempt to replace MSI interrupts to specific cores on the AM5728, I've been trying to use FPGA writes over PCIe into the Mailbox module to trigger interrupts, but have been unable to trigger an IRQ. If I manually write to the Mailbox message queue location in software, the IRQ occurs, so I know I have that part set up correctly. I also already have been doing PCIe writes into DSP1's L2SRAM via inbound translation. For the mailbox module writes, I set up a new PCIe inbound translation region for the L4_PER3 that MAILBOX2 resides in, but my PCIe writes from the FPGA don't seem to be reaching the mailbox module. I realize that the PCIe master port is mapped to the L3 main interconnect and the mailboxes live in L4. Is there some type of permissions or translation that I need to configure to allow the PCIe to directly access the mailbox module?

Thanks!

Sean

over 5 years ago

0 Sean DeHarde over 5 years ago

Intellectual 315 points

Some more background info:

Instead of adding a new translation region specifically for the L4_PER3 address range, I also attempted to expand my existing region (targeting DSP1 L2SRAM) to cover the L3MAIN address range from 0x40000000-0x4FFFFFFF (which includes both L2SRAM and L4_PER3). PCIe writes into the DSP's memory still worked correctly with this new region but I still can't write to the Mailbox module. The AM571x is the PCIe RC and the FPGA is the PCIe EP.

In my region (inbound region 0) I configure a base low address of 0x10000000, a target low address of 0x40000000, and a size of 0xFFFFFFF in memory matching mode. On the FPGA, writing to L2SRAM via an address of 0x10812190 works correctly, translating to an address of 0x40812190. Writing to the mailbox module via a PCIe address of 0x1883A048, translating to an address of 0x4883A048 (MAILBOX2, message queue 2, message register), does nothing. As I said before, if I write to 0x4883A048 directly in the processor, the message is received the module triggers an IRQ as expected.

My PCIe rejection range is configured as 0x20000000-0x40000000 (the addresses of the EP BARs I have configured). Help!