PROCESSOR-SDK-DRA8X-TDA4X: MCU R5F Vector Table Relocate

mallikarjun gattam

Part Number: PROCESSOR-SDK-DRA8X-TDA4X

Hi Team,

We are working on R5F core 0 in MCU island.

We have following vector table mapped to BTCM start address (0x41010000) and we are booting our binary using SPL. hence ATCM is disabled.

But by default processor will look into "0x00" location for vector table. Now we want to change this location to BTCM start address. Please provides us the information on relocating the vector table address.

.sect   ".rstvectors"

_resetvectors: .asmfunc
    LDR pc, c_int00_addr        ; Reset
    LDR pc, undefInst_addr      ; Undefined Instruction
    LDR pc, swi_addr            ; Software interrupt
    LDR pc, preAbort_addr       ; Abort (prefetch)
    LDR pc, dataAbort_addr      ; Abort (data)
    LDR pc, rsvd_addr            ; rsvd
    LDR pc, irq_addr             ; IRQ
    LDR pc, fiq_addr             ; FIQ
    .endasmfunc

Regards,

Mallikarjun

over 5 years ago

0 mallikarjun gattam over 5 years ago

Intellectual 470 points

Hi Team,

PFA. linker used.

/* Linker Settings                                                            */
/* Standard linker options						      */
--retain="*(.bootCode)"
--retain="*(.startupCode)"
--retain="*(.startupData)"
--fill_value=0
--stack_size=0x2000
--heap_size=0x1000

-stack  0x2000                              /* SOFTWARE STACK SIZE           */
-heap   0x2000                              /* HEAP AREA SIZE                */

--define FILL_PATTERN=0xFEAA55EF
--define FILL_LENGTH=0x100

__IRQ_STACK_SIZE = 0x2000;
__FIQ_STACK_SIZE = 0x2000;
__ABORT_STACK_SIZE = 0x1000;
__UND_STACK_SIZE = 0x1000;
__SVC_STACK_SIZE = 0x1000;

#define DDR0_ALLOCATED_START 0xA0000000

#define MCU1_0_EXT_DATA_BASE     (DDR0_ALLOCATED_START + 0x00100000)
#define MCU1_0_R5F_MEM_TEXT_BASE (DDR0_ALLOCATED_START + 0x00200000)
#define MCU1_0_R5F_MEM_DATA_BASE (DDR0_ALLOCATED_START + 0x00300000)
#define MCU1_0_DDR_SPACE_BASE    (DDR0_ALLOCATED_START + 0x00400000)
#define ATCM_START 0x00000000
#define BTCM_START 0x41010000

/*-e __VECS_ENTRY_POINT */ /*commented as it is not used in classic stack*/

--entry_point=_resetvectors     /* Default C RTS boot.asm   */
/*----------------------------------------------------------------------------*/
/* Memory Map                                                                 */
MEMORY
{
    /* MCU1_R5F_0 local view  */
    MCU_ATCM (RWX)		: origin=ATCM_START	length=0x8000
    /* MCU1_R5F0_TCMB0 (RWIX)	: origin=BTCM_START	length=0x8000 (documented only, to avoid conflict below) */

    /* MCU1_R5F_0 SoC view  */
    MCU1_R5F0_ATCM (RWIX)  	: origin=0x41000000 length=0x8000
    MCU1_R5F0_BTCM_VECS (RWIX)  : origin=0x41010000 length=0x0100
    MCU1_R5F0_BTCM (RWIX) 	: origin=0x41010100 length=0x7F00

    DDR0_RESERVED    (RWIX)  	: origin=0x80000000 length=0x20000000	  	/* 512MB */
    MCU1_0_IPC_DATA (RWIX)	: origin=DDR0_ALLOCATED_START     length=0x00100000	/*   1MB */
    MCU1_0_EXT_DATA  (RWIX)	: origin=MCU1_0_EXT_DATA_BASE     length=0x00100000	/*   1MB */
    MCU1_0_R5F_MEM_TEXT (RWIX)	: origin=MCU1_0_R5F_MEM_TEXT_BASE length=0x00100000	/*   1MB */
    MCU1_0_R5F_MEM_DATA (RWIX)	: origin=MCU1_0_R5F_MEM_DATA_BASE length=0x00100000	/*   1MB */
    MCU1_0_DDR_SPACE (RWIX)	: origin=MCU1_0_DDR_SPACE_BASE    length=0x00C00000	/*  12MB */

    SHARED_DDR_SPACE (RWIX)	: origin=0xAA000000 length=0x01C00000           /*  28MB */

}  /* end of MEMORY */

/*----------------------------------------------------------------------------*/
/* Section Configuration                                                      */

SECTIONS
{
	.rstvectors     : {} palign(8) > MCU1_R5F0_BTCM_VECS
    .bootCode    	: {} palign(8) 		> MCU1_R5F0_BTCM
    .startupCode 	: {} palign(8) 		> MCU1_R5F0_BTCM
	.OS_CODE		: {} palign(8)   	>MCU1_R5F0_BTCM
    .startupData 	: {} palign(8) 		> MCU1_R5F0_BTCM, type = NOINIT
    .text	: {} palign(8)		> MCU1_0_DDR_SPACE
    
    /*AUTOSAR code section starts*/    
    .CODE 			: {} palign(8)   	>MCU1_0_DDR_SPACE
    .CALLOUT_CODE   : {} palign(8)   	>MCU1_0_DDR_SPACE
    .const   	: {} palign(4) 		> MCU1_0_DDR_SPACE
    
     /*AUTOSAR code section starts*/
     .CONST_32                                    : {} palign(4) 		> MCU1_0_DDR_SPACE
     .CONST_16                                    : {} palign(4) 		> MCU1_0_DDR_SPACE
     .CONST_8                                     : {} palign(4) 		> MCU1_0_DDR_SPACE
     .CONST_UNSPECIFIED                           : {} palign(4) 		> MCU1_0_DDR_SPACE
     .CONST_BOOLEAN                               : {} palign(4) 		> MCU1_0_DDR_SPACE
     .CONST_SAVED_RECOVERY_ZONE_16                : {} palign(4) 		> MCU1_0_DDR_SPACE
     .CONST_SAVED_RECOVERY_ZONE_8                 : {} palign(4) 		> MCU1_0_DDR_SPACE
     .CONST_SAVED_RECOVERY_ZONE_32                : {} palign(4) 		> MCU1_0_DDR_SPACE
     .CONST_SAVED_RECOVERY_ZONE_UNSPECIFIED       : {} palign(4) 		> MCU1_0_DDR_SPACE
     .CONST_SAVED_RECOVERY_ZONE_BOOLEAN           : {} palign(4) 		> MCU1_0_DDR_SPACE
     
     
    .cinit   	: {} palign(8) 		> MCU1_0_DDR_SPACE
    .pinit   	: {} palign(8) 		> MCU1_0_DDR_SPACE
    .bss     	: {} align(4)  		> MCU1_0_DDR_SPACE
    
    /*AUTOSAR uninitialised/cleared Data section starts*/
    .VAR_NO_INIT_32											 > MCU1_0_DDR_SPACE
    .VAR_SAVED_ZONE_32										 > MCU1_0_DDR_SPACE
    .VAR_FAST_NO_INIT_32									 > MCU1_0_DDR_SPACE
    .VAR_NO_INIT_16											 > MCU1_0_DDR_SPACE
    .VAR_SAVED_ZONE_16										 > MCU1_0_DDR_SPACE
    .VAR_FAST_NO_INIT_16									 > MCU1_0_DDR_SPACE
    .VAR_NO_INIT_8											 > MCU1_0_DDR_SPACE
    .VAR_SAVED_ZONE_8										 > MCU1_0_DDR_SPACE
    .VAR_FAST_NO_INIT_8										 > MCU1_0_DDR_SPACE
    .VAR_SAVED_ZONE_BOOLEAN									 > MCU1_0_DDR_SPACE			
    .VAR_NO_INIT_BOOLEAN									 > MCU1_0_DDR_SPACE
    .VAR_NO_INIT_UNSPECIFIED_RAM							 > MCU1_0_DDR_SPACE
    .VAR_NO_INIT_STACK_CORE1_UNSPECIFIED					 > MCU1_0_DDR_SPACE
    .VAR_FAST_NO_INIT_BOOLEAN								 > MCU1_0_DDR_SPACE
    .VAR_NO_INIT_UNSPECIFIED								 > MCU1_0_DDR_SPACE
    .VAR_SAVED_ZONE_UNSPECIFIED								 > MCU1_0_DDR_SPACE
    .VAR_FAST_NO_INIT_UNSPECIFIED							 > MCU1_0_DDR_SPACE
    .VAR_CLEARED_32											 > MCU1_0_DDR_SPACE
    .VAR_POWER_ON_CLEARED_32								 > MCU1_0_DDR_SPACE
    .VAR_FAST_CLEARED_32									 > MCU1_0_DDR_SPACE
    .VAR_CLEARED_16											 > MCU1_0_DDR_SPACE
    .VAR_POWER_ON_CLEARED_16								 > MCU1_0_DDR_SPACE
    .VAR_FAST_CLEARED_16									 > MCU1_0_DDR_SPACE
    .VAR_CLEARED_8											 > MCU1_0_DDR_SPACE
    .VAR_POWER_ON_CLEARED_8									 > MCU1_0_DDR_SPACE
    .VAR_FAST_CLEARED_8										 > MCU1_0_DDR_SPACE
    .VAR_CLEARED_BOOLEAN									 > MCU1_0_DDR_SPACE
    .VAR_POWER_ON_CLEARED_BOOLEAN							 > MCU1_0_DDR_SPACE
    .VAR_FAST_CLEARED_BOOLEAN								 > MCU1_0_DDR_SPACE
    .VAR_CLEARED_UNSPECIFIED								 > MCU1_0_DDR_SPACE
    .VAR_POWER_ON_CLEARED_UNSPECIFIED						 > MCU1_0_DDR_SPACE
    .VAR_FAST_CLEARED_UNSPECIFIED							 > MCU1_0_DDR_SPACE
    .VAR_NO_INIT_STACK_UNSPECIFIED                    		 > MCU1_0_DDR_SPACE
    .VAR_NO_INIT_UNSPECIFIED_STACK							 > MCU1_0_DDR_SPACE
	
    
    .data    	: {} palign(128) 	> MCU1_0_DDR_SPACE
    
    /*AUTOSAR Data section starts*/
    .VAR_INIT_32											 > MCU1_0_DDR_SPACE
    .VAR_POWER_ON_INIT_32									 > MCU1_0_DDR_SPACE
    .VAR_FAST_INIT_32										 > MCU1_0_DDR_SPACE
    .VAR_INIT_16											 > MCU1_0_DDR_SPACE
    .VAR_POWER_ON_INIT_16									 > MCU1_0_DDR_SPACE
    .VAR_FAST_INIT_16										 > MCU1_0_DDR_SPACE
    .VAR_INIT_8												 > MCU1_0_DDR_SPACE
    .VAR_POWER_ON_INIT_8									 > MCU1_0_DDR_SPACE
    .VAR_FAST_INIT_8										 > MCU1_0_DDR_SPACE
    .VAR_INIT_BOOLEAN										 > MCU1_0_DDR_SPACE
    .VAR_POWER_ON_INIT_BOOLEAN								 > MCU1_0_DDR_SPACE
    .VAR_FAST_INIT_BOOLEAN									 > MCU1_0_DDR_SPACE
    .VAR_INIT_UNSPECIFIED									 > MCU1_0_DDR_SPACE
    .VAR_POWER_ON_INIT_UNSPECIFIED							 > MCU1_0_DDR_SPACE
    .VAR_FAST_INIT_UNSPECIFIED								 > MCU1_0_DDR_SPACE

    
    .CONFIG_DATA_8                    			  : {} palign(4) 		> MCU1_0_DDR_SPACE
    .CONFIG_DATA_16                   			  : {} palign(4) 		> MCU1_0_DDR_SPACE
    .CONFIG_DATA_32                   		 	  : {} palign(4) 		> MCU1_0_DDR_SPACE
    .CONFIG_DATA_BOOLEAN                   	  	  : {} palign(4) 		> MCU1_0_DDR_SPACE
    .CONFIG_DATA_UNSPECIFIED                 	  : {} palign(4) 		> MCU1_0_DDR_SPACE
    .CONFIG_CONST_UNSPECIFIED_ROM                 : {} palign(4) 		> MCU1_0_DDR_SPACE
    .CONFIG_DATA_8_RAM                 		      : {} palign(4) 		> MCU1_0_DDR_SPACE
    .CONFIG_DATA_UNSPECIFIED_RAM                  : {} palign(4) 		> MCU1_0_DDR_SPACE

    
    .data_buffer: {} palign(128) 	> MCU1_0_DDR_SPACE
    .sysmem  	: {} 			> MCU1_0_DDR_SPACE
    .stack	: {} align(4)		> MCU1_0_DDR_SPACE
    ipc_data_buffer (NOINIT) : {} palign(128)	> MCU1_0_DDR_SPACE
    .resource_table : {
        __RESOURCE_TABLE = .;
    } > MCU1_0_EXT_DATA_BASE

    .tracebuf   : {}			> MCU1_0_EXT_DATA
	
    /*Shared Memory*/
    .Kcdd_Ipc_HeaderIfo_Sec		>SHARED_DDR_SPACE
    .Kcdd_Ipc_Ch1_RBuf_Sec		>SHARED_DDR_SPACE
    .Kcdd_Ipc_Ch1_TBuf_Sec		>SHARED_DDR_SPACE
	


    /* Additional sections settings     */
      McalNoInitSection : fill=FILL_PATTERN, align=4, load > MCU1_0_DDR_SPACE, type = NOINIT
    {
        .=align(4);
        __linker_can_no_init_start = .;
        . += FILL_LENGTH;
        *(CAN_DATA_NO_INIT_UNSPECIFIED_SECTION)
        *(CAN_DATA_NO_INIT_32_SECTION)
        .=align(4);
        . += FILL_LENGTH;
        __linker_can_no_init_end = .;		
		 // __linker_cdd_ipc_no_init_start = .;
        // . += FILL_LENGTH;
        // *(CDD_IPC_DATA_NO_INIT_UNSPECIFIED_SECTION)
       /* *(CDD_IPC_DATA_NO_INIT_8_SECTION)*/
        // .=align(4);
        // . += FILL_LENGTH;
        // __linker_cdd_ipc_no_init_end = .;
	}	
	
	// VariablesAlignedNoInitSection : align=8, load > MCU1_0_DDR_SPACE, type = NOINIT
    // {
        // .=align(8);
        // __linker_cdd_ipc_no_init_align_8b_start = .;
        // . += FILL_LENGTH;
        // *(CDD_IPC_DATA_NO_INIT_8_ALIGN_8B_SECTION)
        // .=align(8);
        // . += FILL_LENGTH;
        // __linker_cdd_ipc_no_init_align_8b_end = .;
    // }
	
    McalInitSection : fill=FILL_PATTERN, align=4, load > MCU1_0_DDR_SPACE
    { 
        .=align(4);
        __linker_can_init_start = .;
        . += FILL_LENGTH;
        *(CAN_DATA_INIT_8_SECTION)
        .=align(4);
        . += FILL_LENGTH;
        __linker_can_init_end = .;
		
		
		 // .=align(4);
        // __linker_cdd_ipc_init_start = .;
        // . += FILL_LENGTH;
        /* *(CDD_IPC_DATA_INIT_UNSPECIFIED_SECTION) */
        // *(CDD_IPC_DATA_INIT_32_SECTION)
        /* *(CDD_IPC_DATA_INIT_8_SECTION) */
        // .=align(4);
        // . += FILL_LENGTH;
        // __linker_cdd_ipc_init_end = .;
		
		
    }	
    McalConstSection : fill=FILL_PATTERN, align=4, load > MCU1_0_DDR_SPACE
    {	
	        .=align(4);
        __linker_dio_const_start = .;
        . += FILL_LENGTH;
        *(DIO_CONST_32_SECTION)
        .=align(4);
        . += FILL_LENGTH;
        __linker_dio_const_end = .;
		
        .=align(4);
        __linker_can_const_start = .;
        . += FILL_LENGTH;
        *(CAN_CONST_8_SECTION)
        *(CAN_CONFIG_SECTION)
        .=align(4);
        . += FILL_LENGTH;
        __linker_can_const_end = .;	
		 // .=align(4);
        // __linker_cdd_ipc_const_start = .;
        // . += FILL_LENGTH;
        // /* *(CDD_IPC_CONST_32_SECTION) */
        // *(CDD_IPC_CONFIG_SECTION)
        // .=align(4);
        // . += FILL_LENGTH;
        // __linker_cdd_ipc_const_end = .; 
	}
    /* Additional sections settings     */
    McalTextSection : fill=FILL_PATTERN, align=4, load > MCU1_0_DDR_SPACE
    {
        .=align(4);
        __linker_can_text_start = .;
        . += FILL_LENGTH;
        *(CAN_TEXT_SECTION)
        *(CAN_ISR_TEXT_SECTION)
        .=align(4);
        . += FILL_LENGTH;
        __linker_can_text_end = .;
		
        .=align(4);
        __linker_dio_text_start = .;
        . += FILL_LENGTH;
        *(DIO_TEXT_SECTION)
        .=align(4);
        . += FILL_LENGTH;
        __linker_dio_text_end = .;	
		// .=align(4);
        // __linker_cdd_ipc_text_start = .;
        // . += FILL_LENGTH;
        // *(CDD_IPC_TEXT_SECTION)
        // *(CDD_IPC_ISR_TEXT_SECTION)
        // .=align(4);
        // . += FILL_LENGTH;
        // __linker_cdd_ipc_text_end = .;
    }
    
   /*Start up settings*/ 
    .irqStack   : {. = . + __IRQ_STACK_SIZE;} align(4)      >MCU1_0_DDR_SPACE
    RUN_START(__IRQ_STACK_START)
    RUN_END(__IRQ_STACK_END)
    .fiqStack   : {. = . + __FIQ_STACK_SIZE;} align(4)      >MCU1_0_DDR_SPACE
    RUN_START(__FIQ_STACK_START)
    RUN_END(__FIQ_STACK_END)
    .abortStack     : {. = . + __ABORT_STACK_SIZE;} align(4)    >MCU1_0_DDR_SPACE
    RUN_START(__ABORT_STACK_START)
    RUN_END(__ABORT_STACK_END)
    .undStack   : {. = . + __UND_STACK_SIZE;} align(4)      >MCU1_0_DDR_SPACE
    RUN_START(__UND_STACK_START)
    RUN_END(__UND_STACK_END)
    .svcStack   : {. = . + __SVC_STACK_SIZE;} align(4)      >MCU1_0_DDR_SPACE
    RUN_START(__SVC_STACK_START)
    RUN_END(__SVC_STACK_END)

}  /* end of SECTIONS */

/*----------------------------------------------------------------------------*/
/* Misc linker settings                                                       */


/*-------------------------------- END ---------------------------------------*/

Regards,

Mallikarjun

0 mallikarjun gattam over 5 years ago in reply to mallikarjun gattam

Intellectual 470 points

Hello,

With above Linker, the stack is working fine in Debugger mode.
We are able to receive and transmit CAN frames.

But in SD card mode no interrupts are getting generated.

Therefore, we wanted to know what settings are done during CCS Debugger flash (gel file to flash) and SD boot mode?

Regards,
Mallikarjun

0 Brijesh Jadav over 5 years ago in reply to mallikarjun gattam

TI__Guru**** 489055 points

Hi Malikarjun,

Does the polling mode work fine? Can you please check the status bit and confirm it received data correctly?

Rgds,

Brijesh

0 mallikarjun gattam over 5 years ago in reply to Brijesh Jadav

Intellectual 470 points

Hello Brijesh,

We have Integrated our Autosar OS in the stack.
In Debugger mode OS timer interrupt and other interrupts are working fine.
In SD card mode none of the interrupts are getting generated. (Note: This not only with respect to CAN interrupts)

So, we wanted understand if any extra configuration is done to the core while loading the binary?

Regards,
Mallikarjun

0 Brijesh Jadav over 5 years ago in reply to mallikarjun gattam

TI__Guru**** 489055 points

Malikarjun,

When you call sciclient API to request irq number, do you request specific number or any interrupt?

Rgds,

Brijesh

0 mallikarjun gattam over 5 years ago in reply to Brijesh Jadav

Intellectual 470 points

Hello Brijesh,

We are using CSL APIs to set and manage Interrupts. Yes, we do request specific interrupt numbers for a particular to interrupt to be configured.

We are not using sciclient APIs to set or configure interrupts.

Regards,

Mallikarjun

0 Brijesh Jadav over 5 years ago in reply to mallikarjun gattam

TI__Guru**** 489055 points

Malikarjun,

For which modules interrupts are not working?

For few modules, interrupt is directly connected, but for rest, we have to use SciClient API, without calling it, interrupt will not work..

Rgds,

Brijesh

0 mallikarjun gattam over 5 years ago in reply to Brijesh Jadav

Intellectual 470 points

Brijesh,

Interrupts that we want to use on peripherals.

MCU timer interrupts
MCU CAN RX and TX

We are using SVC software interrupt as well in OS.

Without debugger only SVC interrupt is getting generated.

Regards,

Mallikarjun

0 Brijesh Jadav over 5 years ago in reply to mallikarjun gattam

TI__Guru**** 489055 points

Hi Malikarjun,

For CCS, which core are using? and when core are you using for SD mode?

For cross domain access of the CAN module and other modules, you need to call sciclient API..

Regards,

Brijesh

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PROCESSOR-SDK-DRA8X-TDA4X: MCU R5F Vector Table Relocate