AM3352: Questions about the DDR PHY Control Registers

UNA

Part Number: AM3352

Hi,

I have questions about DDR PHY controller for AM335x

Q1: WR_DQS_SLAVE_RATIO_CS0 seems to be the amount of shift of the DQS signal from the DQ signal output at write access.
Which signal does WR_DATA_SLAVE_RATIO_CS0 indicate the amount of shift?

Q2: What is the meaning of the DATA0/DATA1_REG_PHY_DQ_OFFSET_0 register setting value?

Q3：What is the meaning of the RD_DQS_SLAVE_RATIO_CS0 register setting value?
　　What is the relationship between the master DLL and the slave DLL as described in the description of this register?

Q4：The reset value of DATA0_REG_PHY_RD_DQS_SLAVE_RATIO _0 is listed in Table 7-260 as 0x04010040.
On the other hand, the reset value is different from the one shown in Figure 7-245; what is the difference?

Best Regards,
H.U

over 5 years ago

0 Andreas Dannenberg over 5 years ago

TI__Guru 69582 points

H.U,

please allow for a couple of days to get back on this (holiday weekend here). Will look into this early/mid next week.

Regards, Andreas

0 UNA over 5 years ago in reply to Andreas Dannenberg

Mastermind 7980 points

Hi Andreas,

I have been waiting to hear from you.
If the investigation will take a long time, please let me know.

Best Regards,
H.U

IDEC AUTO ID Solutions

0 Andreas Dannenberg over 5 years ago in reply to UNA

TI__Guru 69582 points

H.U,

this request was assigned to our DDR expert recently, and he'll work with you on this directly here very soon. Thanks for your patience.

Regards, Andreas

0 UNA over 5 years ago in reply to Andreas Dannenberg

Mastermind 7980 points

Hi Andreas,

These are questions from my customer and they are in a hurry.
I understand that you are very busy, but I am looking forward to your soonest reply.

Best Regards,
H.U

0 Andreas Dannenberg over 5 years ago in reply to UNA

TI__Guru 69582 points

H.U,

UNA said:
I understand that you are very busy, but I am looking forward to your soonest reply.

This question was assigned to our DDR expert a few days back. I just checked today but he is out of the office this week. I've also reached out to two other engineers to see if they can help but have not heard back yet. Worst-case it might be early next week before we can get back on this.

Regards, Andreas

0 JJD over 5 years ago in reply to Andreas Dannenberg

TI__Guru* 85960 points

the customer should not be concerned with the details of all of the PHY registers, as they should not be individually altering these registers. They should be using the AM335x EMIF tool https://www.ti.com/lit/pdf/sprack4 to configure the DDR Controller/PHY. All of the registers you mention will be properly configured after the customer fills out the spreadsheet in the EMIF tool

Regards,

James

0 UNA over 5 years ago in reply to JJD

Mastermind 7980 points

Hi James,

Thank you for your reply.

The customer is using the AM335x EMIF tool to set the registers. They are asking for details on these registers to adjust the signal quality/timings.
Could you answer again for Q1 through Q4?

Best Regards,
H.U

0 JJD over 5 years ago in reply to UNA

TI__Guru* 85960 points

We don't recommend individually adjusting these registers. The tool should give optimal values for both SI and timing as long as the design guidelines from the datasheet were followed. If there is something specific they are trying to debug, we can try to help with that, but we would need to start with the results of the EMIF tool

Regards,

James

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AM3352: Questions about the DDR PHY Control Registers