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EVMK2H: Input CLK of DSP and ARM

Chanh Nguyen64
Expert 1230 points

Part Number: EVMK2H

Hi all,

I am setting up the new EVM board (Rev 4.0).

I set SW1 to be - 4(ON) 3(ON) 2(ON) 1(OFF) >> DSP No Boot mode. So It is the Sleep Boot mode, right?

Then I read the DEVSTAT register, the value is 0x2000001, if I decode the DEVSTAT by the SLEEP boot mode, the ARM PLL Config and SYS PLL Config are 0b000. So the input CLK Freq is 50 MHz. It is not what I know because for K2H the input CLK should be 122.88 for DSP, Am I correct? And for ARM I see in the GEL file the default option is 125MHz, but previous board my reading from DEVSTAT is 122.88 MHz.

 Could you please advise how to understand the Input Clock Freq to set the correct clock for DSP and ARM in GEL?

Thanks.

  • 0
    TI__Mastermind 42545 points

    Hi Chanh,

    The clocking for the K2H EVM is provided by two CDCM62008 which are programmed by the BMC microcontroller.   The CDCM62008 provides 125MHz as a clock input for the ARM_CLK, 122.88MHz for the SYS_CLK and 125MHz for the ALT_CORE_CLK.  The DEV STAT register value defines the PLLs as disabled and the CORECLKSEL as 0 so the ARM PLL will be in bypass and the ARM will be clocked at 125MHz and the SYS PLL will bypass the SYS_CLK running at 122.88MHz.  The bootmode can be read from the BMC using the COM port routed to the FTDI mini-USB interface.  If you enter the command bootmode, the BMC will display the value that it should present to the bootmode pins.  Can you determine the bootmode value programmed into the BMC for both of your boards?

    Regards, Bill

  • 0 in reply to Bill Taboada
    Expert 1230 points

    Hi Bill,

    For my new board, I set the switch to be SW1 - 1(OFF) 2(OFF) 3(OFF) 4(ON), the boot mode is as below:

    For my previous board, when I check the DevStat, I set the Switch to be SW1 - 4(ON) 3(ON) 2(ON) 1(OFF), the bootmode is as below:

    I also try to change the switch on old board to SW1 - 1(OFF) 2(OFF) 3(OFF) 4(ON), and the bootmode is as below:

    Seems for both boards, when the swith is 1(OFF) 2(OFF) 3(OFF) 4(ON), they have the same DevStat value 0x02000001. Can I understand from your reply that for this bootmode, ARM will be clocked at 125MHz and SYS_CLK running at 122.88MHz?

    Thanks.

  • 0 in reply to Chanh Nguyen64
    TI__Mastermind 42545 points

    Hi Chanh,

    That is correct.  The PLLs will be in bypass so the input clock frequencies should be used by the ARM and System subsections.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Expert 1230 points

    Got it. Thanks Bill.