Part Number: AM6548
In the attached dump of AM65x/DRA80xM DDR Board Design and Layout Guidelines (Rev. A),
what does the highlighted point want to say?
Trace width of single-ended signal & differential signal should be the same or not?
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Part Number: AM6548
In the attached dump of AM65x/DRA80xM DDR Board Design and Layout Guidelines (Rev. A),
what does the highlighted point want to say?
Trace width of single-ended signal & differential signal should be the same or not?
It is making a generalization - if you have a single-end 50-ohm trace that is 5mils width...then two 5mil traces with spacing of 10+mil should be about 100-ohm differential impedance. It is not recommended to design a PCB based on this generalization. Rather - contact your PCB manufacturer and have them provide you exact trace width/spacing for your target impedance(s).
Thanks Robert for your valuable info & time.Scan 11-Jul-2020.pdf
Is it necessary to keep the trace width of differential nets as of single ended trace to match Zdiff = 2 X Z0.
Because if I create tightly coupled differential pair, then 100 OHM impedance is achieved with smaller trace width.
See attached documented StackUP for more info.
This is interface dependent, and driven from spec. For example, MIPI CSI2 spec has both singled ended and differential specification for its signals. Many other interfaces only spec the differential impedance.
We typically recommend loosely coupled for differential signals - as its much easier to maintain accurate impedance as the traces cross the PCB. In slight variance in the routing of tightly coupled signals can change the impedance.
Thanks Robert,
That's great help.
Is DDR4 CLK & Strobe signals are also required to match single eneded impedance ?