Hi,
The board uses TI AM 5726 and the GMAC associated MDIO channel connected to an Ethernet's switch MDIO/SMI. There is no PHY on this MDIO / SMI bus. The switch has a very large register address space and implements an indirect register addressing with addresses 0-7 reserved for this purpose.
MDIO / SMI register address 0 and 1 are the 32 bit pointer for the write operation, register address 2 and 3 are the 32 bit data to write, register address 4 and 5 are the 32 bit address to read from, and register address 6 and 7 are the 32 bit data read registers. An operation (read/write) status register is located at register address 0x1F .
The switch is mapped at MDIO/SMI PHY address 0.
Is there a method to stop the MDIO scanning and still be able to issue read/write transactions to access the switch?
If scanning can't be stopped, is there a method to limit the address range where this automatic scanning occurs ? (to prevent interference with switch operation)
Which PHY register is the MDIO scanning ?
Thank you
