AM6548: SERDES0_REFCLK for PCIe3.0 x2 applications

Francesco Lussignoli1

Part Number: AM6548

Hi all,

I'm designing a custom board for a PCIe3.0 x2 applications. I've seen from the TRM that I can do an internal clock sharing to provide both the serdes modules the 100 MHz reference clock (took from the main pll output).

Reading page 149 of the AM654x Datasheet seems that the SERDES0/1 REFCLK P/N clock inputs are mandatory for PCIe applications.

In my opinion I do not need to provide these clocks as I already provide them internally to both serdes modules. Am I missing something?

Thank you in advance for your help ;)

F.L.

over 5 years ago

0 jian35385 over 5 years ago

TI__Mastermind 23125 points

FL,

you do not need to use external REFCLK for 2L configuration. The only requirement is that both SERDES macro use the same source that is chained. i.e., you can configure the left SERDES to use a internal refclk then enabled its chaining to the right, then configure the right SERDES to use the left chained SERDES. Diagrams in Figure 12-1856 gives correct configurations for clock muxes.

let me know if you run into any issues.

Regards

jian

0 Francesco Lussignoli1 over 5 years ago in reply to jian35385

Prodigy 110 points

Hi Jian,

thank you for your reply!

So, I can leave SERDES0_REFCLKP/N pins unconnected if I have already provided the 100MHz serdes clock internally (from main PLL output for example), is it correct?

Regards,

Francesco

0 jian35385 over 5 years ago in reply to Francesco Lussignoli1

TI__Mastermind 23125 points

Francesco,

that is correct. Diagrams in:

Figure 12-1856. SerDes Reference Clock Distribution

of the TRM gives correct configurations you will be using. I attached the figures below.

regards

Jian

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AM6548: SERDES0_REFCLK for PCIe3.0 x2 applications