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TDA2x/RTOS: Can't access specify hw register at sometimes

Hi,
I'm working with a TDA2x custom board. (Using VIsionSDK 3.07 Linux+BIOS)

We use Linux mode, but DCAN is set up and used in IPU core.

We access the hardware register directly to use DCAN.
(We're not use DCAN modules included in VisionSDK.)

In DCAN settings, we can access the register without any problems.
After setup, we try DCAN Tx.
But XDC_ASSERT occurs when we access the register(DCAN_IF2CMD). (It's just reading the value.)

Read register code ==========================================================

uint32_t ifRegStatus = HW_RD_REG32(0x4AE3C120);   // TI HW_RD_REG function
Vps_printf("[CAN_TX_DEBUG] DCAN1_IF2CMD: %x \n", ifRegStatus);

=========================================================================

[HOST] [IPU1-0] 66.388702 s: ### XDC ASSERT - ERROR CALLBACK START ###
[HOST] [IPU1-0] 66.388793 s:
[HOST] [IPU1-0] 66.388916 s: E_hardFault: FORCED
[HOST] [IPU1-0] 66.388977 s:
[HOST] [IPU1-0] 66.389007 s: ### XDC ASSERT - ERROR CALLBACK END ###
[HOST] [IPU1-0] 66.389099 s:
[HOST] [IPU1-0] 66.389312 s:
[HOST] [IPU1-0] 66.389343 s: ### XDC ASSERT - ERROR CALLBACK START ###
[HOST] [IPU1-0] 66.389434 s:
[HOST] [IPU1-0] 66.389526 s: E_busFault: PRECISERR: Immediate Bus Fault, exact addr known, address: 4ae3c120
[HOST] [IPU1-0] 66.389648 s:
[HOST] [IPU1-0] 66.389678 s: ### XDC ASSERT - ERROR CALLBACK END ###

=========================================================================

For verification, we tried using DCAN_IF1CMD instead of DCAN_IF2CMD on DCAN1_TX, but the results are the same.
Problem occurs only in Tx on DCAN1. There is no problem with Rx on DCAN1.

This problem occurs at a 90% probability. About 10% works without any problems. So I don't understand.

There is no problem with DCAN2. But we have to use both DCAN1 and 2.

What should I check?

Best regards,
Lee.

  • ++ Update.

    DCAN_IF1CMD was not the only problem.

    All DCAN1-related registers in the DCAN1_Tx function are inaccessible.

    Best regards,
    Lee.

  • Hi, update this thread.

    As mentioned in the previous thread, DCAN1 related register access (R/W) was not available after DCAN INIT.
    My environment is Linux+BIOS, and IPU1_0 core uses DCAN.

    I disabled DCAN in kernel settings, and all problems have been resolved.
    Maybe the problem is caused by CAN0 being activated on Linux.

    I tested it about 30 times, and no XDC_ASSERT occurred.

    Best regards,
    Lee.