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TDA4VMXEVM: Connect a Full HD display to but only VGA(1024x768)

Part Number: TDA4VMXEVM

Hi,

I am trying to connect Full HD display to J7-evm (TDA4VMXEVM, common processor board DISPLAY0 (DP) connector) through the DP-to-miniDP cable. 

I'm using built with PSDKLA 06_01_01_02 version.

Despite being solved in the question here (PSDKLA 06_01_00_05), it is still VGA 1024x768 in 06_01_01_02 version.

If I check resolution mode,

root@j7-evm:~# kmsprint
[ 1700.114791] cdns-mhdp a000000.dp-bridge: [drm:cdns_mhdp_get_edid_block [mhdp8546]] *ERROR* get block[0] edid failed: -22
[ 1700.125650] cdns-mhdp a000000.dp-bridge: [drm:cdns_mhdp_get_modes [mhdp8546]] *ERROR* Failed to read EDID
Connector 0 (35) DP-1 (connected)
  Encoder 0 (34) NONE
    Crtc 0 (33) 1024x768 65.000 1024/24/136/160 768/3/6/29 60 (60.00)
      Plane 0 (28) fb-id: 59 (crtcs: 0) 0,0 1024x768 -> 0,0 1024x768 (AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 AR15 AB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12)
        FB 59 1024x768


root@j7-evm:~# cat /var/volatile/log/weston.log
Date: 2019-12-12 UTC
[21:28:58.595] weston 5.0.0
               wayland.freedesktop.org
               Bug reports to: gitlab.freedesktop.org/.../
               Build: unknown (not built from git or tarball)
[21:28:58.595] Command line: weston --idle-time=0
[21:28:58.595] OS: Linux, 4.19.73-g0cabba2b47, #1 SMP PREEMPT Fri Jul 10 13:53:35 KST 2020, aarch64
[21:28:58.597] Using config file '/etc//weston.ini'
[21:28:58.600] Output repaint window is 7 ms maximum.
[21:28:58.608] Loading module '/usr/lib/libweston-5/drm-backend.so'
[21:28:58.615] initializing drm backend
[21:28:58.703] using /dev/dri/card0
[21:28:58.703] DRM: supports universal planes
[21:28:58.703] DRM: supports atomic modesetting
[21:28:58.703] DRM: supports picture aspect ratio
[21:28:58.706] Loading module '/usr/lib/libweston-5/gl-renderer.so'
...<skip>...
[21:28:59.085] DRM: head 'DP-1' found, connector 35 is connected, EDID make 'unknown', model 'unknown', serial 'unknown'
[21:28:59.085] Registered plugin API 'weston_drm_output_api_v1' of size 24
[21:28:59.085] Chosen EGL config details:
               RGBA bits: 8 8 8 0
               swap interval range: 1 - 1
[21:28:59.085] No backlight control for output 'DP-1'
[21:28:59.085] Output DP-1 (crtc 33) video modes:
               1024x768@60.0, current, 65.0 MHz
               800x600@60.3, 40.0 MHz
               800x600@56.2, 36.0 MHz
               848x480@60.0, 33.8 MHz
               640x480@59.9, 25.2 MHz

Available maximum resolution is 1024x768 only. 

How can i set resolution mode to HD 720p or FHD 1080p ?

If I check loaded driver by "lsmod" command, It can be seen that mhdp8546 driver is loaded. (On target, "/lib/modules/4.19.73-g0cabba2b47/kernel/drivers/gpu/drm/bridge/mhdp8546.ko" ) 

The driver request firmware "/lib/firmware/cadence/mhdp8546.bin" on target, and the firmware it is.

  • Hi Kim,

    Any specific reason for using display on A72?

    We have used DP output from R5F and tested with many DP displays, it works fine. 

    Is it possible to switch to R5F display? are you looking for specific display resolution?

    Rgds,

    Brijesh

  • Hi Brijesh, Thanks for your help.

    I tested PSDKRA 7.0.0 (Linux+RTOS) (on R5F) excuting vision apps, still DP did not working. Nothing is output on display monitor.

    Does the monitor of the table on this thread work only?

    I attach the log message when excuted /opt/vision_apps/vision_apps_init.sh

    root@j7-evm:/opt/vision_apps# source ./vision_apps_init.sh
    root@j7-evm:/opt/vision_apps# [MCU2_0]      0.000000 s: CIO: Init ... Done !!!
    [MCU2_0]      0.000000 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
    [MCU2_0]      0.000000 s: APP: Init ... !!!
    [MCU2_0]      0.000000 s: SCICLIENT: Init ... !!!
    [MCU2_0]      0.000000 s: SCICLIENT: DMSC FW version [20.04.1-v2020.04a (Terrific Lla]
    [MCU2_0]      0.000000 s: SCICLIENT: DMSC FW revision 0x14
    [MCU2_0]      0.000000 s: SCICLIENT: DMSC FW ABI revision 3.0
    [MCU2_0]      0.000000 s: SCICLIENT: Init ... Done !!!
    [MCU2_0]      0.000000 s: UDMA: Init ... !!!
    [MCU2_0]      0.000000 s: UDMA: Init ... Done !!!
    [MCU2_0]      0.000000 s: MEM: Init ... !!!
    [MCU2_0]      0.000000 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2800000 of size 16777216 bytes !!!
    [MCU2_0]      0.000000 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce000000 of size 67108864 bytes !!!
    [MCU2_0]      0.000000 s: MEM: Init ... Done !!!
    [MCU2_0]      0.000000 s: FVID2: Init ... !!!
    [MCU2_0]      0.000000 s: FVID2: Init ... Done !!!
    [MCU2_0]      0.000000 s: VHWA: Init ... !!!
    [MCU2_0]      0.000000 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2
    [MCU2_0]      0.000000 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      0.000000 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2
    [MCU2_0]      0.000000 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      0.000000 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2
    [MCU2_0]      0.000000 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]      0.000000 s: VHWA: DOF Init ... !!!
    [MCU2_0]      0.000000 s: VHWA: DOF Init ... Done !!!
    [MCU2_0]      0.000000 s: VHWA: LDC Init ... !!!
    [MCU2_0]      0.000000 s: VHWA: LDC Init ... Done !!!
    [MCU2_0]      0.000000 s: VHWA: MSC Init ... !!!
    [MCU2_0]      0.000000 s: VHWA: MSC Init ... Done !!!
    [MCU2_0]      0.000000 s: VHWA: NF Init ... !!!
    [MCU2_0]      0.000000 s: VHWA: NF Init ... Done !!!
    [MCU2_0]      0.000000 s: VHWA: SDE Init ... !!!
    [MCU2_0]      0.000000 s: VHWA: SDE Init ... Done !!!
    [MCU2_0]      0.000000 s: VHWA: VISS Init ... !!!
    [MCU2_0]      0.000000 s: VHWA: VISS Init ... Done !!!
    [MCU2_0]      0.000000 s: VHWA: VDEC Init ... !!!
    [MCU2_0]      0.000000 s: VHWA: VDEC Init ... Done !!!
    [MCU2_0]      0.000000 s: VHWA: VENC Init ... !!!
    [MCU2_0]      0.000000 s: VHWA: VENC Init ... Done !!!
    [MCU2_0]      0.000000 s: VHWA: Init ... Done !!!
    [MCU2_0]      0.000000 s: IPC: Init ... !!!
    [MCU2_0]      0.000000 s: IPC: 5 CPUs participating in IPC !!!
    [MCU2_0]      0.000000 s: IPC: Waiting for HLOS to be ready ... !!!
    [MCU2_0]     19.826043 s: IPC: HLOS is ready !!!
    [MCU2_0]     19.831029 s: IPC: Init ... Done !!!
    [MCU2_0]     19.831116 s: APP: Syncing with 4 CPUs ... !!!
    [MCU2_0]     19.831159 s: APP: Syncing with 4 CPUs ... Done !!!
    [MCU2_0]     19.831190 s: REMOTE_SERVICE: Init ... !!!
    [MCU2_0]     19.832482 s: REMOTE_SERVICE: Init ... Done !!!
    [MCU2_0]     19.832538 s: ETHFW: Init ... !!!
    [MCU2_0]     19.904157 s: ETHFW: Version   : 0.01.01
    [MCU2_0]     19.904221 s: ETHFW: Build Date: Jul 23, 2020
    [MCU2_0]     19.904251 s: ETHFW: Build Time: 17:35:52
    [MCU2_0]     19.904272 s: ETHFW: Commit SHA:
    [MCU2_0]     19.904297 s: ETHFW: Init ... DONE !!!
    [MCU2_0]     19.904322 s: ETHFW: Remove server Init ... !!!
    [MCU2_0]     19.948100 s: ETHFW: Remove server Init ... DONE !!!
    [MCU2_0]     19.948174 s: DSS: Init ... !!!
    [MCU2_0]     19.948201 s: DSS: Display type is eDP !!!
    [MCU2_0]     19.948231 s: DSS: SoC init ... !!!
    [MCU2_0]     19.948250 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2
    [MCU2_0]     19.948455 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     19.948485 s: SCICLIENT: Sciclient_pmSetModuleState module=297 state=2
    [MCU2_0]     19.948738 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     19.948765 s: SCICLIENT: Sciclient_pmSetModuleState module=151 state=2
    [MCU2_0]     19.948948 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     19.948978 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=9 parent=11
    [MCU2_0]     19.949066 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
    [MCU2_0]     19.949121 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=13 parent=18
    [MCU2_0]     19.949226 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
    [MCU2_0]     19.949258 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=1 parent=2
    [MCU2_0]     19.949343 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
    [MCU2_0]     19.949372 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk=1 freq=148500000
    [MCU2_0]     19.952062 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
    [MCU2_0]     19.952106 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk=1 state=2 flag=0
    [MCU2_0]     19.952197 s: SCICLIENT: Sciclient_pmModuleClkRequest success
    [MCU2_0]     19.952226 s: DSS: SoC init ... Done !!!
    [MCU2_0]     19.952247 s: DSS: Board init ... !!!
    [MCU2_0]     19.952267 s: DSS: Board init ... Done !!!
    [MCU2_0]     19.969817 s: DSS: Init ... Done !!!
    [MCU2_0]     19.969889 s:  VX_ZONE_INIT:Enabled
    [MCU2_0]     19.969916 s:  VX_ZONE_ERROR:Enabled
    [MCU2_0]     19.969935 s:  VX_ZONE_WARNING:Enabled
    [MCU2_0]     19.973322 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
    [MCU2_0]     19.973368 s: APP: OpenVX Target kernel init ... !!!
    [MCU2_0]     19.980478 s: APP: OpenVX Target kernel init ... Done !!!
    [MCU2_0]     19.980537 s: CSI2RX: Init ... !!!
    [MCU2_0]     19.980562 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
    [MCU2_0]     19.980650 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     19.980682 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2
    [MCU2_0]     19.980824 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     19.980849 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2
    [MCU2_0]     19.980986 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     19.981009 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2
    [MCU2_0]     19.981128 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     19.981162 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2
    [MCU2_0]     19.981254 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     19.981932 s: CSI2RX: Init ... Done !!!
    [MCU2_0]     19.981976 s: CSI2TX: Init ... !!!
    [MCU2_0]     19.981997 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
    [MCU2_0]     19.982110 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     19.982147 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2
    [MCU2_0]     19.982292 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     19.982318 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2
    [MCU2_0]     19.982428 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     19.983015 s: CSI2TX: Init ... Done !!!
    [MCU2_0]     19.983055 s: ISS: Init ... !!!
    [MCU2_0]     19.983146 s: Found sensor IMX390-UB953_D3 at location 0
    [MCU2_0]     19.983210 s: Found sensor AR0233-UB953_MARS at location 1
    [MCU2_0]     19.983255 s: Found sensor AR0820-UB953_LI at location 2
    [MCU2_0]     19.983299 s: Found sensor UB9702_TESTPATTERN at location 3
    [MCU2_0]     19.983326 s: IssSensor_Init ... Done !!!
    [MCU2_0]     19.983401 s: vissRemoteServer_Init ... Done !!!
    [MCU2_0]     19.983453 s: IttRemoteServer_Init ... Done !!!
    [MCU2_0]     19.983477 s: UDMA Copy: Init ... !!!
    [MCU2_0]     19.984757 s: UDMA Copy: Init ... Done !!!
    [MCU2_0]     19.984807 s: APP: Init ... Done !!!
    [MCU2_0]     19.984830 s: APP: Run ... !!!
    [MCU2_0]     19.984852 s: IPC: Starting echo test ...
    [MCU2_0]     19.986792 s: APP: Run ... Done !!!
    [MCU2_0]     19.988027 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] C66X_1[P] C66X_2[.] C7X_1[.]
    [MCU2_0]     19.988227 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] C66X_1[P] C66X_2[P] C7X_1[.]
    [MCU2_0]     19.988343 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] C66X_1[P] C66X_2[P] C7X_1[P]
    [C6x_1 ]      4.239441 s: CIO: Init ... Done !!!
    [C6x_1 ]      4.239473 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>
    [C6x_1 ]      4.239486 s: APP: Init ... !!!
    [C6x_1 ]      4.239493 s: SCICLIENT: Init ... !!!
    [C6x_1 ]      4.239566 s: SCICLIENT: DMSC FW version [20.04.1-v2020.04a (Terrific Lla]
    [C6x_1 ]      4.239579 s: SCICLIENT: DMSC FW revision 0x14
    [C6x_1 ]      4.239587 s: SCICLIENT: DMSC FW ABI revision 3.0
    [C6x_1 ]      4.239597 s: SCICLIENT: Init ... Done !!!
    [C6x_1 ]      4.239605 s: UDMA: Init ... !!!
    [C6x_1 ]      4.240525 s: UDMA: Init ... Done !!!
    [C6x_1 ]      4.240547 s: MEM: Init ... !!!
    [C6x_1 ]      4.240558 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d4000000 of size 16777216 bytes !!!
    [C6x_1 ]      4.240575 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
    [C6x_1 ]      4.240590 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d5000000 of size 50331648 bytes !!!
    [C6x_1 ]      4.240606 s: MEM: Init ... Done !!!
    [C6x_1 ]      4.240614 s: IPC: Init ... !!!
    [C6x_1 ]      4.240625 s: IPC: 5 CPUs participating in IPC !!!
    [C6x_1 ]      4.240637 s: IPC: Waiting for HLOS to be ready ... !!!
    [C6x_1 ]     17.156698 s: IPC: HLOS is ready !!!
    [C6x_1 ]     17.160160 s: IPC: Init ... Done !!!
    [C6x_1 ]     17.160191 s: APP: Syncing with 4 CPUs ... !!!
    [C6x_1 ]     19.831159 s: APP: Syncing with 4 CPUs ... Done !!!
    [C6x_1 ]     19.831173 s: REMOTE_SERVICE: Init ... !!!
    [C6x_1 ]     19.831747 s: REMOTE_SERVICE: Init ... Done !!!
    [C6x_1 ]     19.831784 s:  VX_ZONE_INIT:Enabled
    [C6x_1 ]     19.831794 s:  VX_ZONE_ERROR:Enabled
    [C6x_1 ]     19.831802 s:  VX_ZONE_WARNING:Enabled
    [C6x_1 ]     19.832585 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
    [C6x_1 ]     19.832602 s: APP: OpenVX Target kernel init ... !!!
    [C6x_1 ]     19.832901 s: APP: OpenVX Target kernel init ... Done !!!
    [C6x_1 ]     19.832922 s: UDMA Copy: Init ... !!!
    [C6x_1 ]     19.834795 s: UDMA Copy: Init ... Done !!!
    [C6x_1 ]     19.834814 s: APP: Init ... Done !!!
    [C6x_1 ]     19.835180 s: APP: Run ... !!!
    [C6x_1 ]     19.835192 s: IPC: Starting echo test ...
    [C6x_1 ]     19.836120 s: APP: Run ... Done !!!
    [C6x_1 ]     19.836469 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] C66X_1[s] C66X_2[x] C7X_1[P]
    [C6x_1 ]     19.836690 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] C66X_1[s] C66X_2[P] C7X_1[P]
    [C6x_1 ]     19.987405 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] C66X_1[s] C66X_2[P] C7X_1[P]
    [C6x_2 ]      4.294144 s: CIO: Init ... Done !!!
    [C6x_2 ]      4.294177 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>
    [C6x_2 ]      4.294190 s: APP: Init ... !!!
    [C6x_2 ]      4.294198 s: SCICLIENT: Init ... !!!
    [C6x_2 ]      4.294270 s: SCICLIENT: DMSC FW version [20.04.1-v2020.04a (Terrific Lla]
    [C6x_2 ]      4.294283 s: SCICLIENT: DMSC FW revision 0x14
    [C6x_2 ]      4.294292 s: SCICLIENT: DMSC FW ABI revision 3.0
    [C6x_2 ]      4.294302 s: SCICLIENT: Init ... Done !!!
    [C6x_2 ]      4.294310 s: UDMA: Init ... !!!
    [C6x_2 ]      4.295239 s: UDMA: Init ... Done !!!
    [C6x_2 ]      4.295263 s: MEM: Init ... !!!
    [C6x_2 ]      4.295275 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d8000000 of size 16777216 bytes !!!
    [C6x_2 ]      4.295293 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
    [C6x_2 ]      4.295307 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d9000000 of size 50331648 bytes !!!
    [C6x_2 ]      4.295323 s: MEM: Init ... Done !!!
    [C6x_2 ]      4.295332 s: IPC: Init ... !!!
    [C6x_2 ]      4.295344 s: IPC: 5 CPUs participating in IPC !!!
    [C6x_2 ]      4.295357 s: IPC: Waiting for HLOS to be ready ... !!!
    [C6x_2 ]     17.248776 s: IPC: HLOS is ready !!!
    [C6x_2 ]     17.252437 s: IPC: Init ... Done !!!
    [C6x_2 ]     17.252472 s: APP: Syncing with 4 CPUs ... !!!
    [C6x_2 ]     19.831160 s: APP: Syncing with 4 CPUs ... Done !!!
    [C6x_2 ]     19.831172 s: REMOTE_SERVICE: Init ... !!!
    [C6x_2 ]     19.831752 s: REMOTE_SERVICE: Init ... Done !!!
    [C6x_2 ]     19.831795 s:  VX_ZONE_INIT:Enabled
    [C6x_2 ]     19.831805 s:  VX_ZONE_ERROR:Enabled
    [C6x_2 ]     19.831814 s:  VX_ZONE_WARNING:Enabled
    [C6x_2 ]     19.832584 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
    [C6x_2 ]     19.832601 s: APP: OpenVX Target kernel init ... !!!
    [C6x_2 ]     19.832907 s: APP: OpenVX Target kernel init ... Done !!!
    [C6x_2 ]     19.832928 s: UDMA Copy: Init ... !!!
    [C6x_2 ]     19.834921 s: UDMA Copy: Init ... Done !!!
    [C6x_2 ]     19.834940 s: APP: Init ... Done !!!
    [C6x_2 ]     19.835317 s: APP: Run ... !!!
    [C6x_2 ]     19.835328 s: IPC: Starting echo test ...
    [C6x_2 ]     19.836359 s: APP: Run ... Done !!!
    [C6x_2 ]     19.836694 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] C66X_1[P] C66X_2[s] C7X_1[.]
    [C6x_2 ]     19.836725 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] C66X_1[P] C66X_2[s] C7X_1[P]
    [C6x_2 ]     19.987445 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] C66X_1[P] C66X_2[s] C7X_1[P]
    [C7x_1 ]      4.391348 s: CIO: Init ... Done !!!
    [C7x_1 ]      4.391371 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
    [C7x_1 ]      4.391390 s: APP: Init ... !!!
    [C7x_1 ]      4.391398 s: SCICLIENT: Init ... !!!
    [C7x_1 ]      4.391457 s: SCICLIENT: DMSC FW version [20.04.1-v2020.04a (Terrific Lla]
    [C7x_1 ]      4.391471 s: SCICLIENT: DMSC FW revision 0x14
    [C7x_1 ]      4.391482 s: SCICLIENT: DMSC FW ABI revision 3.0
    [C7x_1 ]      4.391493 s: SCICLIENT: Init ... Done !!!
    [C7x_1 ]      4.391503 s: UDMA: Init ... !!!
    [C7x_1 ]      4.391636 s: UDMA: Init ... Done !!!
    [C7x_1 ]      4.391647 s: MEM: Init ... !!!
    [C7x_1 ]      4.391658 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ dc000000 of size 268435456 bytes !!!
    [C7x_1 ]      4.391682 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!!
    [C7x_1 ]      4.391701 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 491520 bytes !!!
    [C7x_1 ]      4.391718 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!
    [C7x_1 ]      4.391735 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ ec000000 of size 251658240 bytes !!!
    [C7x_1 ]      4.391753 s: MEM: Init ... Done !!!
    [C7x_1 ]      4.391762 s: IPC: Init ... !!!
    [C7x_1 ]      4.391772 s: IPC: 5 CPUs participating in IPC !!!
    [C7x_1 ]      4.391787 s: IPC: Waiting for HLOS to be ready ... !!!
    [C7x_1 ]     17.508799 s: IPC: HLOS is ready !!!
    [C7x_1 ]     17.510967 s: IPC: Init ... Done !!!
    [C7x_1 ]     17.510980 s: APP: Syncing with 4 CPUs ... !!!
    [C7x_1 ]     19.831159 s: APP: Syncing with 4 CPUs ... Done !!!
    [C7x_1 ]     19.831175 s: REMOTE_SERVICE: Init ... !!!
    [C7x_1 ]     19.831473 s: REMOTE_SERVICE: Init ... Done !!!
    [C7x_1 ]     19.831496 s:  VX_ZONE_INIT:Enabled
    [C7x_1 ]     19.831507 s:  VX_ZONE_ERROR:Enabled
    [C7x_1 ]     19.831516 s:  VX_ZONE_WARNING:Enabled
    [C7x_1 ]     19.831731 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
    [C7x_1 ]     19.831745 s: APP: OpenVX Target kernel init ... !!!
    [C7x_1 ]     19.831821 s: APP: OpenVX Target kernel init ... Done !!!
    [C7x_1 ]     19.831839 s: APP: Init ... Done !!!
    [C7x_1 ]     19.831848 s: APP: Run ... !!!
    [C7x_1 ]     19.831857 s: IPC: Starting echo test ...
    [C7x_1 ]     19.832267 s: APP: Run ... Done !!!
    [C7x_1 ]     19.836487 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] C66X_1[P] C66X_2[x] C7X_1[s]
    [C7x_1 ]     19.836715 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] C66X_1[P] C66X_2[P] C7X_1[s]
    [C7x_1 ]     19.987484 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] C66X_1[P] C66X_2[P] C7X_1[s]
    

    log message when excuted /opt/vision_apps/run_app_tidl.sh

    root@j7-evm:/opt/vision_apps# ./run_app_tidl.sh
    APP: Init ... !!!
    MEM: Init ... !!!
    MEM: Initialized DMA HEAP (fd=4) !!!
    MEM: Init ... Done !!!
    IPC: Init ... !!!
    IPC: Init ... Done !!!
    REMOTE_SERVICE: Init ... !!!
    REMOTE_SERVICE: Init ... Done !!!
    APP: Init ... Done !!!
       173.664409 s:  VX_ZONE_INIT:Enabled
       173.664424 s:  VX_ZONE_ERROR:Enabled
       173.664429 s:  VX_ZONE_WARNING:Enabled
       173.664986 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
       173.665154 s:  VX_ZONE_INIT:[tivxHostInit:48] Initialization Done for HOST !!!
    app_tidl: Init ...
    app_tidl: Reading config file /opt/vision_apps/test_data/tivx/tidl_models/tidl_io_mobilenet_v1_1.bin ...
    app_tidl: Reading config file /opt/vision_apps/test_data/tivx/tidl_models/tidl_io_mobilenet_v1_1.bin ... Done. 18056 bytes
    app_tidl: Tensors, input = 1, output = 1
    app_tidl: Reading network file /opt/vision_apps/test_data/tivx/tidl_models/tidl_net_mobilenet_v1.bin ...
    app_tidl: Reading network file /opt/vision_apps/test_data/tivx/tidl_models/tidl_net_mobilenet_v1.bin ... Done. 4469992 bytes
    app_tidl: Init ... Done.
    app_tidl: Creating graph ...
    app_tidl: Creating graph ... Done.
    app_tidl: Verifying graph ...
    app_tidl: Verifying graph ... Done.
    app_tidl: Verifying display graph ...
    app_tidl: Verifying display graph ... Done.
    
    
     =================================
     Demo : TIDL Object Classification
     =================================
    
     p: Print performance statistics
    
     x: Exit
    
     Enter Choice: network file: /opt/vision_apps/test_data/tivx/tidl_models/tidl_net_mobilenet_v1.bin
    config  file: /opt/vision_apps/test_data/tivx/tidl_models/tidl_io_mobilenet_v1_1.bin
    Iteration 0 of 1000000 ...
    

    Regards, 

    Kim

  • Hi Kim,

    For SDK7.0 release, can you uncomment code under '#if 0' at around line number 232 in the psdk_rtos_auto_j7_07_00_00_11\vision_apps\utils\dss\src\app_dss_j721e.c and rebuild sdk and try it out?

    Rgds,

    Brijesh

  • Hi Brijesh,

    Thanks for your help. 

    Your answer solved the problem. 

    Regards,

    Kim