Part Number: AM5718
Hi
I am trying to connect a NAND device on AM5718 custom board
NAND device is currently connected and read and write is successful
But it is not perfect reading and writing
ECC error when rebooting a custom board after writing to NAND
//////////////////////////////////////////////////////////////////////////////////////////////
NAND read: device 0 offset 0x100000, size 0x40000
omap-elm: uncorrectable ECC errors
omap-elm: uncorrectable ECC errors
omap-elm: uncorrectable ECC errors
omap-elm: uncorrectable ECC errors
omap-elm: uncorrectable ECC errors
omap-elm: uncorrectable ECC errors
...
//////////////////////////////////////////////////////////////////////////////////////////////
The NAND device I am using is "MT29F2G08ABAEAWP", and the internal ECC is off.
Must run software ECC.
Therefore, I guess it is a problem in the ECC setting part.
Q1, How to write ECCPOS
(NAND's datasheet? AM5718 TRM?)
/include/configs/am57xx_evm.h
//////////////////////////////////////////////////////////////////////////////////////////////
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
34, 35, 36, 37, 38, 39, 40, 41, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57,}
//////////////////////////////////////////////////////////////////////////////////////////////
Q2, How to set gpmc timing
(I would like to set the gpcm timing. Which document should I refer to?)
arch/arm/dts/am57xx-idk-common.dtsi
//////////////////////////////////////////////////////////////////////////////////////////////
&gpmc {
/*
* For the existing IOdelay configuration via U-Boot we don't
* support NAND on dra7-evm. Keep it disabled. Enabling it
* requires a different configuration by U-Boot.
*/
status = "enabled";
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16 MB */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
gpmc,device-width = <2>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <80>;
gpmc,cs-wr-off-ns = <80>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns=<60>;
gpmc,adv-wr-off-ns=<60>;
gpmc,we-on-ns = <10>;
gpmc,we-off-ns = <50>;
gpmc,oe-on-ns = <4>;
gpmc,oe-off-ns = <40>;
gpmc,access-ns = <40>;
gpmc,wr-access-ns = <80>;
gpmc,rd-cycle-ns = <80>;
gpmc,wr-cycle-ns = <80>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
//////////////////////////////////////////////////////////////////////////////////////////////
Please answer about my question
