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TMS320C6678: C6678 direct SPI boot Problem

Part Number: TMS320C6678


Hi, I used C6678 EMV rev2  and boot my program from spi nor flash by IBL and also direct spi boot (without IBL), every thing is OK,

we designed our c6678 board based on EVM and use  DSP is 1Ghz rev2  and DDR part number (N25Q128) our board is ok and boot program directly from spi properly.

we used DDR Configuration Table: 

00 00 00 70 00 87 35 00 02 42 80 F4 00 00 00 00 00 00 00 00 00 00 00 00 
63 06 2A 32 00 00 00 00 00 00 14 50 11 13 78 3C 30 71 7F E3 55 9F 86 AF 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
00 00 00 00 70 07 32 14 00 00 00 00 00 10 01 0F 00 00 00 00 00 00 00 00 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 05  

based on https://e2e.ti.com/support/processors/f/791/t/430837 and can boot directly from SPI properly.

we also designed a new board but  in new board we use DSP 1.25Ghz rev2 and change the part number of DDR MT25QU128

in this board we just boot from spi by using IBL (I2C boot) and the time of boot ibl is increased to 12sec (we check the i2c clock is 33Khz but in last board this is 187Khz ??!!!  we use crystal 100Mhz in two board)

but we can not boot our program directly from spi nor  ??  when i set boot mode to spi nor flash and it do not boot properly i connect to core0 and check the sections of my program, every sections that was in internal memory copy properly but sections that was in DDR are not copy. i check the ddr address 0x80000000 and saw that the memory change continuously.

  • Please connect to the DSP when boot fails and indicate the value of the program counter. Is the boot failing in ROM bootloader or IBL or in your application Also can you probe the SPI and clockout pin and ensure the clock/data checks out. Read DEVSTAT to ensure that the boot pins are latched correctly as expected.

    Please use the following for additional pointers:

    https://www.ti.com/lit/an/spracn2/spracn2.pdf?ts=1594837655994&ref_url=https%253A%252F%252Fwww.google.com%252F

    If you are connecting to DDR and the memory is continuously changing, this indicates a failure to initialize DDR. Ensure that you have your DDR checkout first using GEL file setting up EMIF and the validate the HW leveling and SDRAM timing settings independent of boot.

    We also provide a system debug GEL file that provides additional debug logs when run from the boot vore:

    3755.Shannon_SystemDebug_v0.4.gel

    Hope this helps.

  • thanks for your reply,

    I check my program counter when boot fail and the PC is 0x82A6596C  ,it seems that  fail on application because the DDR config is not correct.

    I later change the DDR Configuration Table  based on the gel file and  based on the IBL (because it boot correctly from ibl nor flash)     

    but do not boot.  

    DDR Configuration Table dose not explained properly. in table 2-32 page37 in sprs691E configselect is Ambiguous (not  clear )

    can you help me to configure  DDR Configuration Table  properly, because ddr  config in gel file is ok.

    every example referenced in document and e2e forums  the program is in the internal memory and  dont configure DDR and dont use DDR Configuration Table.

  • The issue is definitely with the DDR configuration based on what you have indicated. Our recommendation is to not use the DDR configuration table to setup the DDR for multiple reasons:

    1. DDR configuration sequence was changed after the ROM bootloader implementation was done. 

    2. DDR configuration table for C6678 doesn`t support HW leveling 

    Given the device is booting into secondary bootloader/application. Can you please configure DDR in code in the secondary bootloader or application. YOu can use the DDR configuration sequence in board library for reference:

    pdk_c667x_x_0_xx\packages\ti\board\src\evmC6678\evmC6678_ddr.c

    Hope this helps.

    Regards,

    Rahul