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SYSTEM_RESET_EN is not documented

Yevgeniy Samsonov
Prodigy 50 points
Other Parts Discussed in Thread: TMS320DM365

The TMS320DM365 Silicon Errata document (SPRZ294D) describes the workaround for the VPSS buffer logic reset issue by forcing a watchdog timer reset. The sample code contains references to registers named SYSTEM_RESET_EN and SYSTEM_RESET_TRIGGER located at 0x01C21C08 and 0x01C21C0C (in the Timer 2 config space). But then the SPRUFH0 spec for Timers does not mention any of these addresses as valid registers for Timer 2 and, in fact, describes a completely different process of initializing and arming the WD timer. Which procedure should be used for the VPSS reset workaround - the one described in the Errata doc (implying the corresponding registers do exist but are not documented) or the standard WD init / arming per SPRUFH0?

Thank you,

Eugene Samsonov

  • 0
    TI__Genius 9490 points

    Eugene,

    Good catch :)

    For this workaround please follow the errata.  The reason those 2 registers are not documented in the Timer's userguide is because those registers are the Timers module GPIO registers, and we don't support individual module GPIO modes since we have a sytem GPIO module for the pins that are multiplexed with GPIOs.

    As stated in the errata we are 'forcing' a WD reset in this manner, inside the chip, the WDog timer output signal (not pined out) is connected to the PLL controller reset signal. A practical WDog timer's functionality(as described in the Timer userguide) is for the WDog to time out and to reset the system and the proper init sequence is to be followed.  But since we are trying to achieve a workaround during the boot process(UBL) we are saving CPU boot time by 'forcing' the Watchdog Reset signal, we've tested this workaround and that is why it documented as such and there is no need to document those registers in the Timer userguide but only here in the Errata advisory.

    I hope this helps clarify things.

    regards,

    miguel