AM5K2E04: Keystone II DDR3 Memory Controller: How to test the ECC feature

Hi Rex,

I have a question regarding the operation of ECC when injecting 1-bit error using "ddr" command of U-Boot.

The ECC is enabled for the range 0x80000000 - 0xffffffff (ECC Address Range 1 Register: 0x3fff0000), 1-bit ECC error interrupt is enabled.

The whole memory is initialized with 0x00000000 pattern.

Then I tried to inject 1-bit error using the "ddr" command. I run it 3 times, the results are as follows:

1st time:

# ddr ecc_err 0x80000000 0x1
Disabling DDR ECC ...
ECC err test, addr 0x80000000, read data 0x0, wrote data 0x1, err pattern: 0x1, read after write data 0x1
Enabling DDR ECC ...
ECC err test, addr 0x80000000, read data 0x1
1-bit ECC err count: 0x5
1-bit ECC err address log: 0x39d17040

2nd time:

# ddr ecc_err 0x80000000 0x1
Disabling DDR ECC ...
ECC err test, addr 0x80000000, read data 0x1, wrote data 0x0, err pattern: 0x1, read after write data 0x0
Enabling DDR ECC ...
ECC err test, addr 0x80000000, read data 0x0

3rd time:

# ddr ecc_err 0x80000000 0x1
Disabling DDR ECC ...
ECC err test, addr 0x80000000, read data 0x0, wrote data 0x1, err pattern: 0x1, read after write data 0x1
Enabling DDR ECC ...
ECC err test, addr 0x80000000, read data 0x1
1-bit ECC err count: 0x4
1-bit ECC err address log: 0x3ca48b00

So my questions are:

• Why the output results are different between these tests (there is no 1-bit ECC error report in the second test)?
• When there is 1-bit ECC err report, I saw that the 1-bit ECC err count and err address log are different, why is that?
• I found in the document of DDR3 Memory Controller that the value in the 1-Bit ECC Error Address Log Register displays the first address logged in the 2 deep address logging FIFO? Could you explain the meaning of this? 

Thanks.

Best regards,

Huy

Hi, Huy,

I suspect the data may have changed when you write to the DDR because the ECC was disabled first. After you modified the DDR, then enable the ECC,. The system doesn't know you purposely modified the memory, hence thinks it's an error.

I don't know the answers on top of my head for your other questions. I'll need to spend time to do some reading.

Rex

Hi Rex,

Thank you for your answer. I have spent the last few days, trying to test the operation of the ECC.

Different from last time, I have set the ECC Address Range 1 Register with the value 0x00010000 (ECC covers the smallest memory area which ranges from 0x80000000 - 0x8003FFFF). By this, I can ignore unrelated errors while injecting the ECC bit error to DDR.

Then I tried to inject a 1-bit ECC error at the address 0x80000000 using "ddr" command. But it seems that the ECC cannot detect the error and therefore cannot correct it.

# ddr ecc_err 0x80000000 0x1

Do you have any idea why the ECC cannot detect the error? Or do you have any example related to ECC operation and "ddr" command?

Thank you.

Huy

Hi,  Huy,

Sorry, I've been busy and have not had any chance to look at the issue and done any reading yet. I have all day meeting on Thursday and the earliest I can take a look at it is on Friday. I'll get back to you on this after I get on it.

Rex

Hi, Huy,

How did you set the ECC Address Range 1 register and what value did you program the register with?

Rex

Hi Rex,

I found that the ECC Address Range 1 register can be set in the following method (running command "ddr ecc_err <address> <bit-error>") in cmd_ddr3.c file:

static int ddr_memory_ecc_err(u32 base, u32 address, u32 ecc_err);

__raw_writel(ECC_START_ADDR1 | (ECC_END_ADDR1 << 16), base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);

In the original source code, ECC_END_ADDR1 is defined as follows:

#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - CONFIG_STACKSIZE) >> 17) - 2)

I don't fully understand this definition. What is the purpose of using start address of stack pointer here?

My purpose is the enabled ECC for the memory from 0x80000000 - 0x8003FFFF.

ECC_START_ADDR1 is still the same (0x80000000)

ECC_END_ADDR1 can be defined as:

#define ECC_END_ADDR1       ((0x8003ffff - DDR_REMAP_ADDR) >> 17)

Did I make mistake here?

Huy

Hi, Huy,

In the User's Guide, it says 33-bit address of ECC. You are using 32-bit address.

Rex

Hi Rex,

I have already considered this point. As I mentioned, I would like to enable the ECC for the memory area from 0x0.8000.0000 to 0x0.8003.FFFF

So I think in this case, start address and end address [32-17] of 33-bit addresses for ECC address range are still the same as 32-bit because bit 33th is 0.

The base address of RAM is 0x8000.0000, so in my case the value that needs to be written to the ECC address range 1 register is: 0x00001.0000

Is this correct?

Huy