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AM6548: CPTS event fifo depth

Dominic Rath
Mastermind 7410 points
Part Number: AM6548

Dear TI team,

I've started looking into the CPTS modules in order to achieve time synchronization within the AM65x and in conjunction with an external PCIe RC to which the AM65x is connected as an EP.

One thing that I've been unable to find in the TRM so far is a specification of the depth of the CPTS event FIFOs. The TRM says that the event FIFO needs to be serviced "in a timely manner to prevent FIFO overrun", but fails to say how many entries the FIFO can hold, and what is going to happen if software does NOT service the FIFO fast enough, e.g. whether it stopps accepting new events or if it is going to overwrite old events.

There is figure 11-4. "Event FIFO Misalignment Condition" that seems to suggest that the FIFO is 16 entries deep, but I would like to be sure about that, especially since there are multiple CPTS instances that might well be implemented with different properties.

  • How many entries can the CPTS event FIFO hold, and are there differences between the instances (PCIEn_CPTS, NAVSS0_CPTS, CPSW_CPTS)?
  • What happens in case of an overrun?

Best Regards,

Dominic

  • 0
    TI__Mastermind 23125 points

    Dominic, 

    I just checked our internal docs and it was indicated "at lease as many locations as two times the number of ports plus 6 locations". So I assume it is 20. But will need to check with design team and get back to you. The FIFO depth is a fixed in the design and common to other CPTS modules in the chip. I will also check with overrun behavior. I think it just keep writing to the end of FIFO, as software supposed to empty the FIFO in timely manner. 

    Regards

    JIan

  • 0 in reply to jian35385
    Mastermind 7410 points

    Hello Jian,

    thanks for your feedback. It would be great if you could check with the design team how this was implemented.

    The overrun behaviour isn't that important to me, because the TRM clearly states that software needs to keep up, so to me it's just a matter of determining how fast we need to be.

    Regards,

    Dominic

  • 0 in reply to Dominic Rath
    TI__Mastermind 23125 points

    Dominic, 

    I received the answer:

    "The event fifo depth is 32 for every CPTS instance that I know of.   If the event FIFO is full any new events will be ignored."

    regards

    Jian