Dear TI team,
I've started looking into the CPTS modules in order to achieve time synchronization within the AM65x and in conjunction with an external PCIe RC to which the AM65x is connected as an EP.
One thing that I've been unable to find in the TRM so far is a specification of the depth of the CPTS event FIFOs. The TRM says that the event FIFO needs to be serviced "in a timely manner to prevent FIFO overrun", but fails to say how many entries the FIFO can hold, and what is going to happen if software does NOT service the FIFO fast enough, e.g. whether it stopps accepting new events or if it is going to overwrite old events.
There is figure 11-4. "Event FIFO Misalignment Condition" that seems to suggest that the FIFO is 16 entries deep, but I would like to be sure about that, especially since there are multiple CPTS instances that might well be implemented with different properties.
- How many entries can the CPTS event FIFO hold, and are there differences between the instances (PCIEn_CPTS, NAVSS0_CPTS, CPSW_CPTS)?
- What happens in case of an overrun?
Best Regards,
Dominic
