Other Parts Discussed in Thread: TMS320C5505
Hi:
I am having problems sending data using the VC5504 UART. The UART is programmed for 8 bit data, 9600 baud, and no flow control. Only Rx interrupt is enabled with FIFO trigger level of 1 byte. All the other interrupts are disabled. What I am observing is that there is no activity on the Tx line even though the code is writing data to the THR register. Also the code monitors bit 6 of the LSR register to ensure that both the Tx FIFO and the Tx shift register are empty. The Tx line remains at 3.3V. Another thing that I observed is that even though flow control is disabled and I am expecting both CTS and RTs to be at 0.0V, I am actually observing the RTS line to be at 2.0V and the CTS line is at 0.0V. Could you please help? I don't know why I am not seeing any activity on the Tx. line. I have configured the UART as below.
Thanks a lot.
Cheers,
Mushtaq
void Uart_Config()
{
int i, divisor;
//Enable Clock to UART.
PCGCR1 &= 0xfffb; //Set bit 2 to 0 to enable uart clock.
//Set parallel port to mode 1, i.e. uart,i2s2,i2s3, and spi. (bits 14-12)
//EBSR |= 0x1000; This is done in pwron.c
//Reset uart. CAUTION: This resets uart, spi, i2s2, and i2s3.
PSRCR = 0x0050; //Count of system clock cycles for which SW reset is asserted in the next instruction.
PRCR &= 0x0080; // Reset peripheral group four -- uart, spi, i2s2, and i2s3 (bit 7).
for(i=0;i<50;i++){}; //Wait.
*(ioport unsigned int *)URPECR = 0x1fff; // disable UART Mushtaq 011911 uart Reset uart Tx and Rx.
//Mushtaq 011911 uart This is for testing.
*(ioport unsigned int *)URLCR = 0x03; // 8-bit, no parity checks, 1 stop
//Mushtaq 011911 uart Changed for c5504.CLOCK_CYCLES_PER_UART_SAMPLE changed in sysdef.h
//divisor = (CLOCK_CYCLES_PER_UART_SAMPLE + 8) / 16;
divisor = (CLOCK_CYCLES_PER_UART_SAMPLE) / 16; //Mushtaq 011911 Data sheet formula is (CPU clock)/(Baud rate *16)
//mytemp = divisor;
*(ioport unsigned int *)URDLL = divisor & 0xFF; //lower byte of divisor.
*(ioport unsigned int *)URDLM = (divisor >> 8) & 0xFF; //upper byte of divisor.
// *(ioport unsigned int *)URIER = 0x07; // enable all interrupts (line status, xmit, recv)
*(ioport unsigned int *)URIER = 0x01; // enable only recv interrupt
/*
URFCR FIFO Control Register
| 76 | 54 | 3 | 2 | 1 | 0 |
10 00 1 1 1 1
| | | | | |
| | | | | FIFO enabled
| | | | Clears the receiver FIFO pointer
| | | Clears the transmitter FIFO pointer
| | 1 Required to always write 1 to this bit
| Reserved
Receiver FIFO trigger level. Set to interrupt CPU every 8 bytes.
*/
// *(ioport unsigned int *)URFCR = 0x8F;
//Mushtaq 011911 uart Changed for c5504.
//*(ioport unsigned int *)URFCR = 0x0F; // change recv trigger level to 1 byte.
*(ioport unsigned int *)URFCR = 0x01; // FIFO must be enabled first.
*(ioport unsigned int *)URFCR = 0x07; // Rx trig 1 byte, no dma, FIFOs clear, counters clear.
/*
URLCR Line Control Register
*/
*(ioport unsigned int *)URLCR = 0x03; // 8-bit, no parity checks, 1 stop
/*
URMCR Modem Control Register
*/
*(ioport unsigned int *)URMCR = 0x0000; // No flow, no loopback mode, and RTS disabled
//Mushtaq 011911 uart Output pin PIO2 from BT module is connected to GPIO15. Set GPIO15 as input.
*(ioport unsigned int *)IODIR1 &= ~IN_BT_TO_DSP; // set the GPIO15 direction to input
//Mushtaq 011911 uart Set GPIO16 as input. Because of mistake on schematic GPIO16 is connected to uart CTS.
*(ioport unsigned int *)IODIR2 &= ~IN_GPIO16; // set the GPIO16 direction to input
i = *(ioport unsigned int *)URRBR; //Mushtaq 011911 uart Clear any preexisting characters.
}