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AM3351: uboot ping to remote host failed with host is not alive

Part Number: AM3351

Hi,

I am working on a custom board which is based on TI AM3351 (ZCE package) and the board has been booted up successfully with u-boot (version 1_2018.01-r0) by assuming it is a beaglebone black board.

The CPSW EMAC is configured with RGMII mode by configuring the pin_mux and the gmii_sel register in the board initialization code (board/ti/am335x/board.c).

The CPSW EMAC port 1 (cpsw_emac0) is connected to port 6 of the PHY (Marvell MV88E6176). The MDIO interface is enabled, and I am able to access the PHY/MII registers, and the PHY LAN ports are able to establish links (by auto-negotiation) with a gigabit network hub (1000Mbps and full-duplex)

When try to ping to a remote host, it failed with below error message,

=> setenv ipaddr 10.237.0.18

=> ping 10.237.0.17

ping failed: host 10.237.0.17 is not alive

By looking at the oscilloscope, there is always a 2.5MHz clock signal (data rate 10Mbps) from the RGMII1_TCLK, but there is no signals sent out from the RGMII1-TD0-3 and RCMII1_TCTL.

During ping, the CPSW driver (drivers/net/cpsw.c) is running on the CPSW subsystem and CPDMA is used to send out data to the EMAC. The EMAC RGMII interface operates with forced mode of operation by default, with the GIG, GMII_EN, and FULLDUPLEX bits in MACCONTROL register (0x4a100d84) set to 1. The TX_EN bit in the CPDMA TX_CONTROL register (0x4a100804) is also set to 1.

The ARP request packet is sent from the ping command and placed in the data buffer:

=> md 0x9ffec400

9ffec400: ffffffff 4530ffff d4d39c11 01000608   ......0E........

9ffec410: 04060008 45300100 d4d39c11 1200ed0a   ......0E........

9ffec420: 00000000 ed0a0000 00001100 00000000   ................

9ffec430: 00000000 00000000 00000000 00000000   ................

 

The DMA buffer descriptor at address 0x4a102060 contains the address of the DMA buffer at address 0x9ffec400:

=> md 0x4a102060

4a102060: 00000000 9ffec400 0000003c d000003c   ........<...<...

4a102070: 9ffec400 0000003c 4a102090 0f2e2446   ....<.... .JF$..

The address of the buffer descriptor is then written to the TX0_HDP register and the DMA engine should pick up the data in the data buffer pointed by the buffer descriptor and send it out to the CPSW EMAC. The update of network statistics can be seen in the debugging log below:

cpdma_submit: first packet enqueued

cpdma_submit: hdp: 0x4a100a00 buffer: 0x4a102060

cpdma_submit: later, hdp: 0x4a100a00 buffer: 0x0

cpdma_submit: CPDMA TX control: 0x1

cpdma_submit: mac_control: 0xa3

cpdma_submit: mac_status: 0x80000000

cpdma_submit: good tx frames: 0x9

cpdma_submit: broadcast tx frames: 0x9

cpdma_submit: multicast tx frames: 0x0

cpdma_submit: pause frames: 0x0

cpdma_submit: deferred tx frames: 0x0

cpdma_submit: collisions: 0x0

cpdma_submit: single collision tx frames: 0x0

cpdma_submit: multiple collisions tx frames: 0x0

cpdma_submit: excessive collisions: 0x0

cpdma_submit: late collisions: 0x0

cpdma_submit: tx underrun: 0x0

cpdma_submit: carrier sense error: 0x0

cpdma_submit: tx octets: 0x240

 

However, we are not seeing any signals from the RGMII1 TX data lines and RGMII1_TCTL.

One thing noticed is that, after the buffer descriptor value is written to the TX0_HDP register, the TX0_HDP register does not hold the value for long, it is reset to 0 shortly afterwards, besides, the MACSTATUS register is always at 0x80000000 which indicate the MAC is idle.

Any ideas what could be causing the problems?

Is there any tests I can run to verify the functionality of the CPSW EMAC?

I am using the generic CPSW driver, is there anything else I need to do for getting the RGMII TX interface to work properly?

  • Hi,

    The CPSW-to-external switch is a use case that is not supported by TI. This use case though has been implemented successfully by customers. The only recommendation I have is to work with the switch manufacturer on their driver for Linux and U-Boot for possible suggestions.

    I looked to see if someone has posted anything related to this particular switch on the TI forum and I didn't find any. There are other entries related to external switches though you might find helpful. A site search in case you are unfamiliar can be performed from a google search like this,     site:e2e.ti.com switch ethernet  

    Best Regards,

    Schuyler

  • Hi Schuyler,

    Thanks for the reply and clarifications.

    We will work with the switch vendor for the issues related to their drivers and specifications.

    However, we still have the below question regarding the AM3351 CPSW EMAC:

    During the u-boot ping to a remote host, the debug log shows that, after a DMA buffer descriptor address is written to the TX0_HDP register, the TX0_HDP register does not hold the address value for long, and it's value is set to 0 almost immediately afterwards. Any idea what is causing the HDP register value being cleared? Does that indicate the DMA engine has already send out the data pointed to by the HDP register? Also, when the TX0_HDP register is holding a valid DMA buffer descriptor address, the MACSTATUS register BIT31 (field IDLE) is of value 1 which indicates the MAC is in idle state and is not performing any data transfer, and i am wondering whether this is the reason there is no data sending out from the RGMII TX data lines during ping.

  • Hi, 

    The statistics from your debug is showing that 9 packets were sent from the MAC. Is this code that you added? Are you seeing packets from the link partner perspective using wireshark perhaps?

    As I mentioned earlier TI does not have an external switch on any of the TI evaluation boards. So I am not sure how to interpret what you are seeing. If there was a PHY connected in this example the interaction would be the cpsw would interrogate the PHY and get the link speed and setup the MAC accordingly. Based on what you are seeing the cpsw's attempt to interrogate the PHY is at least not returning the correct link speed since you are expecting the speed to be 1Gbps but only support for 10Mbps.

    Best Regards,

    Schuyler 

  • Hi Schuyler,

    Yes, this is the code I added to the CPSW driver to display the statistics of the Tx frames. I run the tcpdump utility on the remote host that i tried to ping to, but it didn't capture any Tx frames that i tried to send out (to the network interface it is monitoring). 

    During ping, i could see CPDMA send out the ARP request data packets to the CPSW port 1 (from the debugging log) and the network statistics is incrementing, but are not able to see any signals come out from the RGMII1 transmit data lines as well as the transmit control line on the oscilloscope.  I have checked the RGMII1 interface pin muxing in the board initialization codes (board/ti/am335x/board.c) and all the pad offset and mux modes are configured correctly. I tried using the u-boot md utility to dump the control modules registers (for RGMII1 interface) and all the register values are written correctly.

    Previously, the external PHY wasn't set up correctly, after populating the strap registers to set it to RGMII mode, then, start the ping process again, the CPSW MAC is able to pick up the speed and duplexity from the PHY port (and set to 1000Mbps and full-duplex) it connected to, and the RGMII1_TCLK is now sending out a clock signal of frequency 125Mhz.

    The problem I am facing is that, I can always get the RGMII_TCLK clock signal, but i am not able see any data signals come out from

    RGMII1_TD[3:0], and

    RCMII1_TCTL

    during the ping to a remote host.

    As far as I can understand, after the DMA picks up the data and send it out, the subsequent data transfer will be automatically handled by the hardware. In software, i can only trace up to the point the buffer descriptor is written to the HDP and the HDP is cleared when the data transfer is completed. Somehow, I have no idea how to debug why there is no data signals come out from the RGMII1 transmit data lines. I have checked the TX FIFO configurations in the registers, also, i run the loopback test (and I could see the rx frames statistics is incrementing along with that of the Tx frames). Any ideas what else I can do to debug this issue?

    Thank you.

  • Hi Schuyler,

    For your information, below is the pin_mux of the RGMII1 interface:

    static struct module_pin_mux rgmii1_pin_mux[] = {
    {OFFSET(mii1_txen), MODE(2)},                         /* RGMII1_TCTL */
    {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},    /* RGMII1_RCTL */
    {OFFSET(mii1_txd3), MODE(2)},                         /* RGMII1_TD3 */
    {OFFSET(mii1_txd2), MODE(2)},                         /* RGMII1_TD2 */
    {OFFSET(mii1_txd1), MODE(2)},                         /* RGMII1_TD1 */
    {OFFSET(mii1_txd0), MODE(2)},                         /* RGMII1_TD0 */
    {OFFSET(mii1_txclk), MODE(2)},                        /* RGMII1_TCLK */
    {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},   /* RGMII1_RCLK */
    {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},    /* RGMII1_RD3 */
    {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},    /* RGMII1_RD2 */
    {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},    /* RGMII1_RD1 */
    {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},     /* RGMII1_RD0 */
    {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},    /* MDIO_DATA */
    {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},                            /* MDIO_CLK */
    {-1},
    };

    The RGMII1 interface is always work in MAC mode?

    Is it configurable for either MAC or PHY mode?

    The reason I ask is because I want to make sure that RGMII1 is acting as a MAC here.

  • Hi Schuyler,

    I have dumped the AM3351 register contents to confirm the following:

    1.  The gmii_sel register (control module base: 0x44e10000 and register offset: 0x650) is configured to set the CPSW port 1/port2 to RGMII mode and with no internal delay

    => md.b 0x44e10650 1

    44e10650: 3a                                                 :

    =>

    2. The pin mux registers (control module base: 0x44e10000 and register offset: 0x914) of RGMII interface:

    => md.l 0x44e10914 0x0f

    44e10914: 00000002 00000022 00000012 00000012    ...."...........

    44e10924: 00000012 00000012 00000002 00000022    ............"...

    44e10934: 00000022 00000022 00000022 00000022    "..."..."..."...

    44e10944: 00000027 00000030  00000010                   '...0...

    =>

    The RGMII1 pin muxing definitions in board/ti/am335x/board.c:

    static struct module_pin_mux rgmii1_pin_mux[] = {

            {OFFSET(mii1_txen), MODE(2)},                   /* RGMII1_TCTL 0x914 */

            {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},        /* RGMII1_RCTL 0x918 */

            {OFFSET(mii1_txd3), MODE(2)| PULLUP_EN},        /* RGMII1_TD3  0x91C */

            {OFFSET(mii1_txd2), MODE(2) | PULLUP_EN},       /* RGMII1_TD2  0x920 */

            {OFFSET(mii1_txd1), MODE(2) | PULLUP_EN},       /* RGMII1_TD1  0x924 */

            {OFFSET(mii1_txd0), MODE(2) | PULLUP_EN},       /* RGMII1_TD0  0x928 */

            {OFFSET(mii1_txclk), MODE(2)},                             /* RGMII1_TCLK 0x92C */

            {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},       /* RGMII1_RCLK 0x930 */

            {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},        /* RGMII1_RD3  0x934 */

            {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},        /* RGMII1_RD2  0x938 */

            {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},        /* RGMII1_RD1  0x93C */

            {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},        /* RGMII1_RD0  0x940 */

            {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA 0x948 */

            {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},        /* MDIO_CLK 0x94C*/

            {-1},

    };

    One thing noticed is that even I set “PULLUP_EN” to RGMII1_TD3, RGMII1_TD2, RGMII1_TD1, and RGMII1_TD1, these pins are not internally pulled up when u-boot is loaded, and I doubt the above pin muxing is really taking effect.

    What else I could be missing in the configurations to get data send out from RGMII1 interface?

  • Hi, 

    I discussed with an HW apps team member that said if you are seeing a clock and at the speed you expect this is a good indication. At the moment we can't explain why you don't see data being sent out. Especially since the stats block is counting tx packets. Only 1 CPSW port is hooked in this design?

    As I mentioned earlier the interface was designed to work with a PHY. Could you please attach what else is being printed on the console log?  I would like to see the log to see the MDIO interaction. U-Boot does operations in a serial manner, it will first try to check link status before trying to send a packet. Is there a driver for the switch in the u-boot that you are using? 

    Was the schematic submitted to TI for review before being manufacturing the board?

    Best Regards,

    Schuyler

  • Hi,

    Here are a few registers that we would like to dump using the u-boot memory dump command. The version of the u-boot appears to be old and possibly not DT based. Which TI SDK are you basing the work from?

    Best Regards,

    Schuyler

    MAC_SL.MACCONTROL

    MAC.MACSTATUS

    ALE.CONTROL

    ALE.PORTCTL0

    ALE.PORTCTL1

    ALE.PORTCTL2

    CONTROL_MODULE.gmii_sel

    CPSW_WR.RGMII_CTL 

  • Hi,

    Base the work from TI SDK Beaglebone Black

    Checked out Yocto Linux sumo (kernel version 4.15.18)

    Build the U-Boot with command

    $ bitbake u-boot

    Build Configuration:

    BB_VERSION           = "1.38.0"

    BUILD_SYS           = "x86_64-linux"

    NATIVELSBSTRING     = "universal-4.9"

    TARGET_SYS           = "arm-poky-linux-gnueabi"

    MACHINE              = "beaglebone-black"

    DISTRO               = "poky"

    DISTRO_VERSION       = "2.5.3"

    TUNE_FEATURES       = "arm armv7a vfp neon callconvention-hard cortexa8"

    TARGET_FPU           = "hard"

    meta

    meta-poky

    meta-kontron-a200   = "sumo:74023e6136db1bdaf9a1bce1fcf16a56cdec4498"

    meta-oe

    meta-networking

    meta-python

    meta-multimedia     = "sumo:8760facba1bceb299b3613b8955621ddaa3d4c3f"

     

    The dump of the registers are as below:

    MAC_SL.MACCONTROL

    => md.l 0x4a100d84 1

    4a100d84: 000000a1                               ....

    =>

    MAC.MACSTATUS

    => md.l 0x4a100d88 1

    4a100d88: 80000000                               ....

    =>

    ALE.CONTROL

    => md.l 0x4a100d08 1

    4a100d08: 00000000                               ....

    =>

    ALE.PORTCTL0

    => md.l 0x4a100d40 1

    4a100d40: 00000000                               ....

    =>

    ALE.PORTCTL1

    => md.l 0x4a100d44 1

    4a100d44: 00000000                              ....

    =>

    ALE.PORTCTL2

    => md.l 0x4a100d48 1

    4a100d48: 00000000                               ....

    =>

    CONTROL_MODULE.gmii_sel

    => md.l 0x44e10650 1

    44e10650: 0000003a                               :...

    =>

    CPSW_WR.RGMII_CTL 

    => md.l 0x4a101288 1

    4a101288: 00000000                               ....

    =>

  • Hi,

    Was the dump taken before or after the ping command?

    Best Regards,

    Schuyler

  • Hi,

    The previous register dump was taken before the ping command.

    The register dump taken during the ping command:

    MAC_SL.MACCONTROL: 0xa1

    MAC.MACSTATUS: 0x80000018

    ALE.CONTROL: 0x80000000

    ALE.PORTCTL0: 0x3

    ALE.PORTCTL1: 0x3

    ALE.PORTCTL2: 0x0

    CONTROL_MODULE.gmii_sel: 0x3a

    CPSW_WR.RGMII_CTL: 0xd

     

    The register dump taken after the ping command:

    MAC_SL.MACCONTROL

    => md.l 0x4a100d84 1

    4a100d84: 000000a1                               ....

     

    MAC.MACSTATUS

    => md.l 0x4a100d88 1

    4a100d88: 80000018                               ....

     

    ALE.CONTROL

    => md.l 0x4a100d08 1

    4a100d08: 00000000                               ....

     

    ALE.PORTCTL0

    => md.l 0x4a100d40 1

    4a100d40: 00000000                               ....

     

    ALE.PORTCTL1

    => md.l 0x4a100d44 1

    4a100d44: 00000000                               ....

     

    ALE.PORTCTL2

    => md.l 0x4a100d48 1

    4a100d48: 00000000                               ....

     

    CONTROL_MODULE.gmii_sel

    => md.l 0x44e10650 1

    44e10650: 0000003a                               :...

     

    CPSW_WR.RGMII_CTL

    => md.l 0x4a101288 1

    4a101288: 0000000d                               ....

    =>

  • Hi,

     

    The previous register dump was taken before the ping command.

     

    The register dump taken during the ping command:

    MAC_SL.MACCONTROL: 0xa1

    MAC.MACSTATUS: 0x80000018

    ALE.CONTROL: 0x80000000

    ALE.PORTCTL0: 0x3

    ALE.PORTCTL1: 0x3

    ALE.PORTCTL2: 0x0

    CONTROL_MODULE.gmii_sel: 0x3a

    CPSW_WR.RGMII_CTL: 0xd

     

    The register dump taken after the ping command:

    MAC_SL.MACCONTROL

    => md.l 0x4a100d84 1

    4a100d84: 000000a1                               ....

     

    MAC.MACSTATUS

    => md.l 0x4a100d88 1

    4a100d88: 80000018                               ....

     

    ALE.CONTROL

    => md.l 0x4a100d08 1

    4a100d08: 00000000                               ....

     

    ALE.PORTCTL0

    => md.l 0x4a100d40 1

    4a100d40: 00000000                               ....

     

    ALE.PORTCTL1

    => md.l 0x4a100d44 1

    4a100d44: 00000000                              ....

     

    ALE.PORTCTL2

    => md.l 0x4a100d48 1

    4a100d48: 00000000                              ....

     

    CONTROL_MODULE.gmii_sel

    => md.l 0x44e10650 1

    44e10650: 0000003a                               :...

     

    CPSW_WR.RGMII_CTL

    => md.l 0x4a101288 1

    4a101288: 0000000d                              ....

    =>

  • Hi,

     

    The previous register dump was taken before the ping command.

     

    The register dump taken during the ping command:

    MAC_SL.MACCONTROL: 0xa1

    MAC.MACSTATUS: 0x80000018

    ALE.CONTROL: 0x80000000

    ALE.PORTCTL0: 0x3

    ALE.PORTCTL1: 0x3

    ALE.PORTCTL2: 0x0

    CONTROL_MODULE.gmii_sel: 0x3a

    CPSW_WR.RGMII_CTL: 0xd

     

    The register dump taken after the ping command:

    MAC_SL.MACCONTROL

    => md.l 0x4a100d84 1

    4a100d84: 000000a1                               ....

     

    MAC.MACSTATUS

    => md.l 0x4a100d88 1

    4a100d88: 80000018                               ....

     

    ALE.CONTROL

    => md.l 0x4a100d08 1

    4a100d08: 00000000                               ....

     

    ALE.PORTCTL0

    => md.l 0x4a100d40 1

    4a100d40: 00000000                               ....

     

    ALE.PORTCTL1

    => md.l 0x4a100d44 1

    4a100d44: 00000000                              ....

     

    ALE.PORTCTL2

    => md.l 0x4a100d48 1

    4a100d48: 00000000                              ....

     

    CONTROL_MODULE.gmii_sel

    => md.l 0x44e10650 1

    44e10650: 0000003a                               :...

     

    CPSW_WR.RGMII_CTL

    => md.l 0x4a101288 1

    4a101288: 0000000d                              ....

    =>

  • Hi,

     

    The previous register dump was taken before the ping command.

     

    The register dump taken during the ping command:

    MAC_SL.MACCONTROL: 0xa1

    MAC.MACSTATUS: 0x80000018

    ALE.CONTROL: 0x80000000

    ALE.PORTCTL0: 0x3

    ALE.PORTCTL1: 0x3

    ALE.PORTCTL2: 0x0

    CONTROL_MODULE.gmii_sel: 0x3a

    CPSW_WR.RGMII_CTL: 0xd

     

    The register dump taken after the ping command:

    MAC_SL.MACCONTROL

    => md.l 0x4a100d84 1

    4a100d84: 000000a1                               ....

     

    MAC.MACSTATUS

    => md.l 0x4a100d88 1

    4a100d88: 80000018                              ....

     

    ALE.CONTROL

    => md.l 0x4a100d08 1

    4a100d08: 00000000                               ....

     

    ALE.PORTCTL0

    => md.l 0x4a100d40 1

    4a100d40: 00000000                               ....

     

    ALE.PORTCTL1

    => md.l 0x4a100d44 1

    4a100d44: 00000000                              ....

     

    ALE.PORTCTL2

    => md.l 0x4a100d48 1

    4a100d48: 00000000                               ....

     

    CONTROL_MODULE.gmii_sel

    => md.l 0x44e10650 1

    44e10650: 0000003a                               :...

     

    CPSW_WR.RGMII_CTL

    => md.l 0x4a101288 1

    4a101288: 0000000d                              ....

    =>

  • Hi,

    One reason for the packets not being transmitted is due the ALE.PORTCTL registers all being disabled. The host port 0 and which ever port the switch is connected to needs to be enabled. There is some interaction with the switch that makes the driver think the link connection is not active. A team member that I need to discuss with on possible options is not available until next week. 

    Best Regards,

    Schuyler

  • Hi,

    Here is some feedback that we have:

    It looks like the link is at 1G

    1) We are not clear if this is

       MAC-PHY<-->PHY-MAC

       --- or ----

       MAC<-->MAC

    This seems like a MAC<-->MAC, meaning the CPSW to a MAC port of the switch.

     

    2) CONTROL_MODULE.gmii_sel: 0x3a

       Which means "rgmii-id" - PHY provides delays.

       Is this correct? try other options, like "rgmii-rxid"

     

    3) Is Device tree being used? Are you using the driver model for the CPSW?

     

     

    Regarding HDP question - TRM

    ===

    TX Channel (0..7) DMA Head Descriptor Pointer - Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel.

    Writing to these locations when they are non-zero is an error (except at reset).

    Host software must initialize these locations to zero on reset.

    ====

    It's auto reset.

     

    Might help to try also:

    a) ALE_BYPASS.

    b) Start some broadcast traffic towards to board and then run ping to see if RX counter will be incremented.

    c) Confirm that after u-boot up and running ping can pass through two other external ports of the MV88E6176

       (not connected to am335x)

    Best Regards,

    Schuyler