• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 99 subscribers
  • Views 499 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

C6726B Reset problem

Tatiano Busatto
Prodigy 20 points

Other Parts Discussed in Thread: TPS3106

Hello, I'm developing a custom board based on DSP C6726B and am having problems with reset circuit. Sometimes the DSP doesn´t performs the reset on start-up. Also, when I force the reset, it doesn´t happens. The approximate success rate on reset is about 1:2. As you know, that DSP allows two choices of external clock input. In my first board version I used the 3.3V LVCMOS-Compatible external clock oscillator option. In an attempt to correct this problem, in my second hardware version I have included in the circuit described on Silicon Errata SPRZ232F (Figure 21), but contrary to what I expected, the problem with the reset remained the same.

On my third attempt I tried to use the crystal oscillator in place of the LVCMOS oscillator, also I used the suggested circuit on Silicon Errata SPRZ232F (this time, Figure 20). For my unhappiness, nothing has changed. My problem with the RESET remained the same.

I'm currently using the TI TPS72501DT voltage regulators for core supply (1.2V) and for voltage supervisoty circuit, I'm using the TI TPS3106. The attached images show circuit.

I really don't know what else I can do.

If is possible, may you answer the following questions:

1.This problem is common to happen?

2. Has anyone who already faced this situation?

3.Maybe you could give me any tips to fix my problem?

Thanks in advance.

Tatiano.

 

  • 0
    TI__Guru*** 125430 points

    Tatiano,

    The errata you are trying to workaround only affected Rev 1.0 silicon.  Since you are using the part 6726B you have Rev 1.2 silicon which does not have this issue.

    Here's how the data sheet shows the clock input should look:

    If you're using method b, did you make sure to ground OSCIN and to tie OSCVdd to CVdd?

    A couple other things to watch out for:

    • Make sure you have pullups on EMU0 and EMU1 or the device could power up into a boundary scan mode.
    • I recommend an external pulldown on TRST as well.

    Brad

  • 0 in reply to Brad Griffis
    Prodigy 20 points

    Thank you for replying Brad.
     
    About the silicon errata I really don´t realized about the revision. Anyway I already take it off my circuit because it doesn´t improve the reset.

    Both OSCIN and OSCVdd, are conected to ground and CVdd respectively. EMU0, EMU1 and TRST are like you suggested.

    The clock signal on CLKIN pin seems OK (1,36Vpp, offset=1,74V). CVdd is 1.24 V and DVdd is 3.21V. Is there any other points that I can check?

    Thansks,

    Tatiano.

  • 0 in reply to Tatiano Busatto
    TI__Guru*** 125430 points

    Tatiano Busatto said:
    The clock signal on CLKIN pin seems OK (1,36Vpp, offset=1,74V).

    So you're saying your clock signal ranges from 1.06V to 2.42V?  That's definitely not ok...  It should be a square wave from 0.0 to 3.3V.  Unless I've greatly misunderstood what you're saying, I assume that is the root of your issues.