AM5728: Interrupts between PRU-ICSS subsystems

Scott Tancock

Part Number: AM5728
Other Parts Discussed in Thread: AM5729

Hi,

I'm writing an application that requires all 4 of the PRUs on the AM5728 to be synchronised (+= 1 clock cycle) while performing IO (specifically, I've got a 16MHz 48-bit bus to read from, hence all PRUs need to work in sync). I'm attempting to synchronise them with interrupts, and I've been successful within a PRU-ICSS (specifically, between PRUs 2_0 and 2_1). However, I am struggling to get interrupts to trigger between the two PRU subsystems.

I am mapping IRQ ('System Event') 28 to host interrupt 4, and I am triggering IRQ28 manually on PRU2_0 (by writing 28 to the INTC SICR register). I have observed that HI4 is indeed triggering on this PRU (by looking at the HIPIR4 register). I then map PRU-ICSS2_HI4 (IRQ crossbar #198) to system event 38 on PRU-ICSS1 using the configuration register at 0x4A00 28D4 (bits 8:0). Code snippet:

	// Map global interrupt sources
	void *CTRL_CORE_BASE = (void *)0x4A002000;
	uint32_t *p_CTRL_CORE_PRUSS1_IRQ_38_39 = (uint32_t *)(CTRL_CORE_BASE + 0x8D4);
	// Reset
	*p_CTRL_CORE_PRUSS1_IRQ_38_39 = 0;
	// IRQ 38 = PRUSS2_IRQ_HOST4
	*p_CTRL_CORE_PRUSS1_IRQ_38_39 |= 198;
	// IRQ 39 = PRUSS2_IRQ_HOST5
	*p_CTRL_CORE_PRUSS1_IRQ_38_39 |= (199 << 16);

System event 38 (IRQ38) on PRU1_0 is mapped to Host Interrupt 0, and I have confirmed that manually triggering IRQ38 does indeed trigger HI0. Therefore, I believe that my error lies in the mapping of PRU-ICSS2_HI4 to PRU-ICSS1_IRQ38.

Could you please point out what I am missing in order to tie a PRU host interrupt to a PRU IRQ?

Thanks,

Scott

EDIT: Correction: the part number is actually AM5729. The board is a Beaglebone AI Rev.A1

over 5 years ago

0 Stanley Liu over 5 years ago

TI__Guru 50045 points

Hi Scott,

Your cross bar configuration looks correct.

To enable System Event 38 to trigger interrupt on PRU-ICSS1, you have to map it to one of the 10 interupt channels.

Did you map System event 38 to one of the interrupt channel in PRU-ICSS1 PRUSS_INTC_CMR9 register?

Regards,
Stanley

0 Scott Tancock over 5 years ago in reply to Stanley Liu

Prodigy 60 points

Hi Stanley,

I believe I have mapped it. I use CMR9_bit.CH_MAP_38 to map channel 38 to host interrupt 0 and I also write 38 to the ESIR register. Here's the corresponding code:

	// Map CH0 to HI0 and CH1 to HI1
	// -> Should already be done by resource table...
	//CT_INTC.HMR0_bit.HINT_MAP_0 = 0;
	//CT_INTC.HMR0_bit.HINT_MAP_1 = 1;
	
	// Map CH4 to HI4 and CH5 to HI5
	CT_INTC.HMR1_bit.HINT_MAP_4 = 4;
	CT_INTC.HMR1_bit.HINT_MAP_5 = 5;
	
	// Map interrupts 28 and 29 (7_0 and 7_1) to host interrupts 4 and 5.
	CT_INTC.CMR7_bit.CH_MAP_28 = 4;
	CT_INTC.CMR7_bit.CH_MAP_29 = 5;
	// Map interrupts 38 and 39 (9_2 and 9_3) to host interrupts 0 and 1.
	CT_INTC.CMR9_bit.CH_MAP_38 = 0;
	CT_INTC.CMR9_bit.CH_MAP_39 = 1;
	
	// Enable interrupt sources 28 and 29 (prX_pru_mst_intr[12,13]_intr_req)
	CT_INTC.EISR_bit.ENABLE_SET_INDEX = 28;
	CT_INTC.EISR_bit.ENABLE_SET_INDEX = 29;
	// Enable interrupt sources 38 and 39
	CT_INTC.EISR_bit.ENABLE_SET_INDEX = 38;
	CT_INTC.EISR_bit.ENABLE_SET_INDEX = 39;
	
	// Enable host interrupts 1, 4 and 5
	
	// HI0 and HI1 act as the actual interrupt bit for PRUs 0 and 1
	// -> Should already be done by resource table
	CT_INTC.HIEISR_bit.HINT_ENABLE_SET_INDEX = 0;
	CT_INTC.HIEISR_bit.HINT_ENABLE_SET_INDEX = 1;
	
	// HI4 and HI5 loop back onto internal interrupts 20 and 21.
	CT_INTC.HIEISR_bit.HINT_ENABLE_SET_INDEX = 4;
	CT_INTC.HIEISR_bit.HINT_ENABLE_SET_INDEX = 5;
	
	// Map global interrupt sources
	void *CTRL_CORE_BASE = (void *)0x4A002000;
	uint32_t *p_CTRL_CORE_PRUSS1_IRQ_38_39 = (uint32_t *)(CTRL_CORE_BASE + 0x8D4);
	// Reset
	*p_CTRL_CORE_PRUSS1_IRQ_38_39 = 0;
	// IRQ 38 = PRUSS2_IRQ_HOST4
	*p_CTRL_CORE_PRUSS1_IRQ_38_39 |= 198;
	// IRQ 39 = PRUSS2_IRQ_HOST5
	*p_CTRL_CORE_PRUSS1_IRQ_38_39 |= (199 << 16);

Regards,

Scott

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AM5728: Interrupts between PRU-ICSS subsystems