Flashing NANDEBOOT to OMAP-L138 using PB

Hi,

Just I rebuilt the UBL in CCS and flashed the AIS Binary and EBOOTNANDFLASH.nb0 using SFH.

observed that the UBL is getting the Maginum 0x55424CBB from block 6 to 8.

Where as EBOOT is updating itself from Block Number: 2

The header also differe that is written by SFH and EBOOT.

Nand Boot Header in UBL for loading EBOOT was defined as

typedef struct _NANDBOOT_HEADER_
{
  Uint32 magicNum;    // Expected magic number
  Uint32 entryPoint;  // Entry point of the user application
  Uint32 numPage;     // Number of pages where boot loader is stored
  Uint32 block;       // Starting block number where User boot loader is stored
  Uint32 page;        // Starting page number where boot-loader is stored
  Uint32 ldAddress;   // Starting RAM address where image is to copied - XIP Mode
}
NANDBOOT_HeaderObj,*NANDBOOT_HeaderHandle;

where as in Windows CE the boot header is as follows

 const BOOT_HEADER f_BootHdr ={ // Magic number

0xA1ACED11,

Hi,

I had modified the BOOT_HEADER to be compatible with the BOOT_HEADER structure defined in CCS ARM UBL Code.

In WinCE EBOOT flash.c I have defined the BOOT_HEADER as below

magicnum = 0x55424CBB, entryPoint = 0xC7F60000, numpage = 0x80, block = 0x02, page = 0x01, ldAddress = 0xC7F60000

I have changed only one parameter that is setting block = 2 instead of 6 as set by SFH.

Before updating EBOOT I was reading the Flash Contents First sector from the first 40 blocks.

What I had observed is EBOOT not able to read the blocks 6, 7 and 8 and displays the below text message

FMD_ReadSector: Failed to read sector 0x180
 Failure, sector read failed

Where as for blocks 2, 3 and 4 contains the data 0xFFFFFFFF only

After updating EBOOT using Platform Builder if I read the first sector of Block 2, 3 and 4 it contains the data other than 0xFFFFFFFF.

With blocks 6, 7 and 8 the read is failed.

Why EBOOT not able to read the data written by SFH?

To modify EBOOT so that it can read the EBOOT written by SFH what I need to implement?

Thank You & Regards,

GSR

Hello GSR,

Could the eboot read failure of blocks 6, 7 and 8 be an ECC issue?  

You should be able to verify this by recompiling your eboot with this line comment out  "set BSP_ENABLE_NAND_ECC=1" in PLATFORM\OMAPL138_AM18X\OMAPL138_AM18X.bat.

This way, when the eboot reads, it will not verify ECC and should be able to read blocks 6,7 and 8.  

If the read failure is because of ECC, then for some reason the ECC written by sfh is different from the ECC calculated by eboot.

Also, when you can read blocks 2, 3 and 4, can you verify the data read back is the same as that written?  

Thanks,

WM

Hi WM,

Thank You for the reply.

• When I modify set BSP_ENABLE_NAND_ECC= in the .bat file then the EBOOT able to read block 6, 7 and 8.
• I am trying to understand the ECC layout written by sfh and the EBOOT
• When I read blocks 2, 3 and 4 the read data matches with the written data.

Regards,

GSR

Hi,

As part of having feature of updating EBOOT from PB, I am trying to understand the NAND Routines.

The BSP that I am using is BSP_WINCE_ARM9_01_00_02.

FMD_WriteSector and FMD_ReadSector calls RdPageInfo and WrPageInfo whenever pSectorInfoBuf is not NULL.

For RdPageInfo and WrPageInfo the arguments are address of osi structure and FlashBase Address.

In nand_asm.s the RdPageInfo code is as follows

LEAF_ENTRY RdPageInfo

stmfd sp!,{r1 - r5}  ; Push R1, R2, R3, R4 and R5 contents to SP

ldmia r1!, {r4 - r5} ; Load R4 and R5 with [R1] and [R1 + 4] respectively. R1 incremented by 8 (Read from FlashBaseAddrData Pointer)

; In above code my doubt is we always need to read from the Nand Flash Base while reading data right? But we are reading the second word from (Nand Flash Base Addr + 4) is it not an issue?

stmia r0!, {r4 - r5} ; Load [R0] = R4 and [R0 + 4] = R5 , R0 incremented by 8  (Write to OSI Destination Structure)

subs r1, r1, #8 ; R1 = R1 - 8; here NandFlashBase Pointer decremented by 8 so again it moves to FlashBaseAddr.

ldr r4, [r1] ; Load R4 with [R1]

str r4, [r0] ; Store R4 contents to [R0]

Another doubt that I am having is the data bus is 8-bit but we are writing 32-bit value how it will be converted to 4, 8-bit transactions.

Can some one please clarify the same.

Thank You & Regards,

GSR

Hi Atul,

Thank you for the reply.

Why EBOOT and SFH are following two different NAND Boot headers while writing EBOOT.?

If we have to have EBOOT updating itself then do we have to follow the headet written by SFH or headet that is written by EBOOT?

Regards,

GSR

Hi Atul,

Thank you for replying and for the answer.

Regards,

GSR