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SRIO Links

Michael Markov
Intellectual 370 points


Hello,

 

We are working on connecting C6455 and Xilinx Virtex5 sx through

SRIO on a custom board. We are able to establish connection and

transmit some data at 125 Mhz, 1.25 Gbps in single lane

mode. 

 

Unfortunately we have some problems with stability, namely in some

cases links are not getting up after power on. We tried to reset SRIO

on FPGA side following example design when links are up and data

transfer is ok but after reset DSP SRIO controller enters error state

(input or output stop state). If we try to copy FPGA's expected

inbound ACKID in DSP outbound and outstanding ACKID then data transfer

works sometimes for a while but eventually get I OUTPUT_RETRY_STP

(which can not be reset) or other stop conditions that reappear after

I reset them.

 

I would greately appreciate any advice on how to solve the reset

problem or what could be a reson for down links after power up (links

are up most of the time after power up).

 

Thanks in advance

  • 0
    Intellectual 370 points

    My problem was in JTAG, when its clock has been connected to the ground, problem with SRIO LINKS disappeared.

  • 0 in reply to Michael Markov
    TI__Mastermind 18256 points

    Hi,

    this is documented in the errata. See http://www.ti.com/litv/pdf/sprz234n

     

    Advisory 3.1.21 Potential SerDes Clocking Issue

    Revision(s) Affected: 3.1 and earlier

    Details: An issue has been found in the SerDes interfaces that causes a SerDes clocking
    problem in normal functional operation. This problem will not occur when external
    pull-down is applied on the TCK pin (JTAG controller clock). SerDes are used in the
    Serial RapidIO interface (SRIO).
    The TCK pin (JTAG controller clock) is internally assigned to an internal signal that is
    used by the SerDes macro. For the SerDes macro to get proper clocking in the normal
    functional operation, it needs the internal signal to be held low. However, there is an
    internal pull-up on the TCK, creating problems for SerDes operation. This problem exists
    on all SerDes interfaces.

    Workaround(s): The TCK pin should be externally pulled down with a 1-kΩ resistor.

     

    Kind regards,

    one and zero