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OMAP-L138 deepsleep pin as input

CHli
Intellectual 330 points 
 
Hi, 

We developed a custom board based on the OMAP-L138. 

Since we need to be able to wake-up from an external event as well as 
from an rtc alarm we attached some logic and an external RTC to the 
deepsleep pin. 

The DEEPSLEEP pin is configured in the PINMUX as an INPUT (value 0 in 
PINMUX0_31_28). We also disable the internal RTC by writing a 1 in the 
RTCDISABLE bit in the control register (CTRL) and setting the SPLITPOWER 
bit as well. 

We have no problem going to sleep and waking up, so far so good. 

But after some investigation about an excessive power consumption issue 
we observed that the DEEPSLEEP pin seems to be DRIVING the signal low 
even tho it's configured as an INPUT. Is that normal ? Is there a 
problem there ? 

Coincidentally the documentation says : 

P.35 of sprs586b.pdf 

3.9.4 DEEPSLEEP Power Control 

Description : DEEPSLEEP power control output

But it is described as an INPUT on the same line. 

Any thought on that ? 

Best regards,
Christophe Aeschlimann
  • 0
    TI__Guru* 83825 points

    Hi Christophe

    Is it possible for you to measure current going into or out of the deepsleep pin while your TTL driver is driving high and driving low.

    Regards

    Mukul

  • 0 in reply to Mukul Bhatnagar
    Intellectual 330 points
    On behalf on my colleague : 
    Hello Mr Bhatnagar,

I am a hardware engineer working with Christophe and would like to 
forward you some more details I sent today to our TI representative 
who unfortunately is currently not in the office.

Measuring the current into the pin would be very difficult due
to the size of BGA and fine pitch components on the DEEPSLEEP
signal.  However, we can guess its in the range 50-100mA based
upon what the driver and OMAP can drive under near short
circuit conditions, i.e. High level output driving a low
level output.  Certainly its enough to pull our 3.3V (200mA)
supply down to ~2.7V.

Many thanks

Charles Thornton
    Mail sent to our representative : 
    From: Charles Thornton
Sent: Mittwoch, 9. Februar 2011 14:32
To: TI Representative

Subject: Re: OMAP-L138 DEEPSLEEP pin always being driven.

Thank you for you reply,

I have further information which may help you understand the
issues. We have an NC7SV74K8X (7474 flip flop) which drives
its 'Q' output directly onto the DEEPSLEEP pin of the OMAP.
Software will clear/set the flip flop output to force the
OMAP to Sleep/Wake-up as required. I decided to monitor the
situation with the DEEPSLEEP pin at the time of power-up
and notice something very strange.

Our understanding from the data sheet is that this pin by
default is an input yet we notice that shortly after power
(all supplies and last supply is 3.3V is ready) is valid on
the OMAP it drives DEEPSLEEP low for ~350mS? Also, it does not
do this all the time, its worse when the OMAP is cold (at
room temperature or when cooler spray cooled).  When the
OMAP has warmed up a little we almost never observe this effect.
It also varies from OMAP to OMAP how often we see this.

Attached are pictures showing the effect.  It shows our TTL
flip flop signal which is connected to OMAP DEEPSLEEP and
the OMAP reset signal which is coming from our TPS65023
power management chip and indicates when all supplies are valid.

1) "q driving DEEPSLEEP good.jpg", this picture shows the
DEEPSLEEP signal going high, then 179mS later OMAP reset is
removed, no problem, all correct, warm conditions.

2) "q driving DEEPSLEEP bad.jpg", this picture shows DEEPSLEEP
being heavily loaded and pulled down after 20mS of 3.3V
becoming valid and is pulled down to 2.7V for 350mS.
Then 178mS later (after the 3.3V pull down) reset is removed.

Both conditions are observed on the same board and this is
using the OMAP-L138 revision 2.0

The main problem for us is that the 3.3V LDO of the
TPS65023 power management chip is being excursively overloaded
during this driver  "short-circuit" time and we have observed
that when the OMAP is kept cold it never gets out of reset due to
the 3.3V being pulled down (out of specification limits for
TPS65023 power good) and it never recovers while the board is cold.

Conclusion:
Why does the OMAP drive the DEEPSLEEP pin active low during a
reset condition?

I hope you can help us.

Charles Thornton

    At the top is what is referenced as : "q driving DEEPSLEEP good.jpg"
At the bottom is what is referenced as  "q driving DEEPSLEEP bad.jpg"

Best regards,

Christophe
  • 0 in reply to CHli
    TI__Guru* 83825 points

    Hi Charles

    Is the problem that you are observing only during power up? It should be clear that the Deep Sleep mode usage assumes that the device is stable/powered up, not during power supply ramp up etc?

    Assuming you are aware of this, I think what you are saying/seeing is that your DeepSleep pin control logic is not behaving as per expectations during power supply ramp up? In general during power up the following is true for most pins on the device

    IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used.

     

    Can you share with us the portion of the schematics for DeepSleep Pin control? I am assuming you are not using any additional functions mux'd with the Deep Sleep pin? You can share the schematics with us via the TI field team also , if you don't want to post on the forum.

    Regards

    Mukul