Part Number: TMS320C6748
I need help with ibis model of TMS320C6748EZWTD4. While simulating General Batch wizard in Hyperlynx for DSP to DRAM DDR interface, we are failing Signal Quality for every nets. Its showing threshold cross failed.
While doing interactive simulation for single net, You can see green net which is at transmit end i.e. DSP, it’s not crossing threshold in one go. But at receive end i.e. Red waveform is quiet good.
We have doubt on ibis model for TMS320C6748EZWTD4.
Assigning model for TMS320C6748EZWTD4, we are getting selector as NOSR0_NOTERM_1P8.
In ibis editor, we can see Model_Type as 3-state.
Request you to please check our issues and update us with correct ibis model for the same and let us know why we are facing signal quality issues at transmit end – DSP.
Also provide us JEDEC standard timing models for DSP to DRAM so that we can able to run DDRx Batch Simulation.
I worked as a Hardware Design engineer in Honeywell Aerospace.
You can reach me to my company mail also: Deepeshwar.Kumar@Honeywell.com
Thanks and Regards,
Deepeshwar
