TDA4VM: dma alignement

Colombo Carlo

Part Number: TDA4VM

Hi everybody

In the TDA4VM processor, what are the alignment requirements of all DMA transactions between DDR DRAM and C6 or C7 DSPs? It seems that they should be aligned to and multiple of 128 bytes, is this correct?

thks

Carlo

over 5 years ago

0 Karan Saxena over 5 years ago

TI__Guru* 78125 points

Hi Carlo,

I'm checking this with the HW team that is this a hard requirement or a recommended requirement to get better performance.

Regards,

Karan

0 Karan Saxena over 5 years ago in reply to Karan Saxena

TI__Guru* 78125 points

Hi Carlo,

I checked with the team and it is not a hard requirement but a recommended requirement to get better performance.

Regards,

Karan

0 Colombo Carlo over 5 years ago in reply to Karan Saxena

TI__Mastermind 25205 points

HI Karan

Thanks for the info. Would you have some numbers of performance vs transfer size? Let's say from 4 B to 1 MB in multiples of 2 or 4.

best regards

Carlo

0 Karan Saxena over 5 years ago in reply to Colombo Carlo

TI__Guru* 78125 points

Hi Carlo,

Shared something over email.

Regards,

Karan

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TDA4VM: dma alignement