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TDA4VM: TDA4VM: Question on pin mux and using dual RMII Ethernet PHY's

tshelbur
Intellectual 1310 points
Part Number: TDA4VM

If I have 2 phys that interface to the MAIN domain on TDA4VM in RMII mode. Each PHY has an output reference clock for TX and RX. Note that the TDA4 has only one clock reference input in the main domain. What do I need to do in regards to the second reference clock from the second RMII PHY if they both need to be connected to the MAIN domain?

  • 0
    TI__Guru 54422 points

    Tom,

    I've pinged a few people for additional feedback.  

    The RMII timings in our Datasheet are timed relative to REF_CLK input so if the two PHYs aren't synchronized in theory the timing may violate the Datasheet for one of the RMII interfaces.

    What is the PHY part number in use?  Can one of them take an input REF_CLK?  Or is there a way to synchronize the two PHYs?

    Thanks,

    Kyle

  • 0
    TI__Genius 16916 points

    Can one or both of the PHYs use the clock as an input instead of an output?  If so, an external clock gen could be used to feed all three clock inputs.  Alternatively, the output clock from one of the PHYs could be fanned out to both the SoC and the other PHY.

  • 0 in reply to B.C.
    TI__Intellectual 1310 points

    Kyle,

    The customer has confirmed with Marvell the PHY vendor that a shared REFCLK configuration will not work on their devices. The interface clocks at 50 MHz so setup and hold times are a concern without independent clocks per the picture below.

  • 0 in reply to tshelbur
    TI__Guru 54422 points

    Tom, 

    What frequency is the oscillator?  If it's just digital logic passing through a 50 MHz oscillator to the RCLK then maybe the two interfaces will be reasonably well synchronized.  If there's any PLL involved then likely the synchronization couldn't be guaranteed.  This would need to be confirmed by Marvell.

    Regards,

    Kyle