AM3352: How to use Spread Spectrum Clocking function?

The best way to reduce radiated emissions is by implementing good design practices when routing signal across PCBs and through cables and/or connectors. Maintaining constant low impedance signal paths with low loop inductance is very important for minimizing radiated emissions. This can be more effective than enabling SSC.

Enabling SSC spreads radiated emissions across a wider spectrum and is commonly used to make it easier to pass radiated emission testing. In my opinion this does not technically reduce emissions, it just makes it harder to measure. SSC may have value since it constantly changes the frequency of emissions which reduces the probability of it creating a problem for another device.

Enabling SSC may not resolve your issue if radiated emissions from the LCD is interfering with another system, but it may help you pass EMI testing if that is your only concern.

This topic is discussed in the "Spread Spectrum Clocking (SSC)" section of the AM335x TRM.

I will need to get someone from one of our software teams to answer your question related to enabling SSC. Which software are you using?

Regards,
Paul

Hi Sir

We used Vxworks as our product OS.

Firstly,  we want to know how to set the register(enable SSC ) to slove the LCD（50Mhz） Radiated Issue in AM3358BZCZA80.

Hello,

Please note that TI only supports TI software on the forums. I have reassigned this to a member of our RTOS team, but we may be limited in the support we can provide.

Regards,

Nick

Are you certain that the LCD is the source of the EMI problem?  How do you know the problem is at 50MHz (are you running pixel clock at 50MHz) ?  Are there any other 50MHz sources on the board?  As explained earlier, SSC changes the frequency of the clock signal to spread the energy across multiple frequencies.  What is the tolerance of the clock input which will be affected by SSC?  Also, how much power reduction are you looking to achieve (in dB)?

Regards,

James 

After we did the Radiated Emission test, we found the points(over the limit ) is about 100Mhz, 

Our LCD pixel is running at 50Mhz(300Mhz/6) we tried not to plug the LCD cable, the result  is pass.

So, we assume that is the reason. 

Regarding to the tolerance, I check the pixel range is 44.9Mhz~63Mhz.

We hope it can reduce above 3dB .

Thanks.

Hi,

the SSC values can be calculated based on the instructions found in section 8.1.6.6 of the TRM.  However, since there are some complicated formulas, i have a crude spreadsheet to help with the calculations.  Can you send me the following registers so i can get the PLL configuration.

0x44E00454

0x44E004A4

Once i get these, i can return the appropriate configuration for the SSC

Regards,

James

James, 

I have a similar case and the PCLK is 30Mhz and require 4 dB reduction.

Here are the clock setting

0x44E00454 : 0x00000903

0x44E004A4 : 0x00000201

Please help to create the SSC register for SSC_DPLL_DISP registers. 

0x44E0044C

0x44E00450 

BR, Rich

Hi James & Rich:

0x44E00454 : 0x00000501 -> for PCLK 30 Mhz.

0x44E004A4 : 0x00000201

I send wrong value.

Sorry for that.

Please help to create the SSC register for SSC_DPLL_DISP registers.

Thanks,

Juncor

Hi Juncor, first, i would recommend to configure the PLL this way

M = 20

N = 0

M2 = 8

This will produce a 60MHz CLKOUT from the PLL.  I assume you have the DISPC_DIVDER set to divide by 2 to achieve 30MHz.  The configuration you had will work, but the above configuration is more optimized for the PLL

For the SSC configuration of 4dB reduction, here are the register settings:

CM_SSC_MODFREQDIV_DPLL_DISP.MODFREQDIV_MANTISSA = 0x65
CM_SSC_MODFREQDIV_DPLL_DISP.MODFREQDIV_EXPONENT = 0


CM_SSC_DELTAMSTEP_DPLL_DISP.DELTAMSTEP_FRACTION =  0x82
CM_SSC_DELTAMSTEP_DPLL_DISP.DELTAMSTEP_INTEGER = 0

Regards,

James

Hi James,

We use the following parameter to set SSC configuration of 4dB reduction.

0x44E00454 : 0x00000501 -> for PCLK 30 Mhz.

0x44E004A4 : 0x00000201

CM_SSC_MODFREQDIV_DPLL_DISP.MODFREQDIV_MANTISSA = 0x65
CM_SSC_MODFREQDIV_DPLL_DISP.MODFREQDIV_EXPONENT = 0


CM_SSC_DELTAMSTEP_DPLL_DISP.DELTAMSTEP_FRACTION =  0x82
CM_SSC_DELTAMSTEP_DPLL_DISP.DELTAMSTEP_INTEGER = 0

The SSC is take effect but we use the Spectrum Analyzer  to  pretest and the result is not good enough.

Please help to create the SSC register for PCLK 30Mhz and require 10 dB reduction.

We wnat to try 10dB SSC register result is better or not. 

Many Thanks,

Ben

Ben, did the settings above actually result in 4dB reduction on the spectrum analyzer?  If not, what was the reduction?

Also, it doesn't look like you changed the PLL configuration as suggested in the earlier post.  Please be sure to change the PLL configuration 

for 10dB reduction:

CM_SSC_MODFREQDIV_DPLL_DISP.MODFREQDIV_MANTISSA = 0x65
CM_SSC_MODFREQDIV_DPLL_DISP.MODFREQDIV_EXPONENT = 2


CM_SSC_DELTAMSTEP_DPLL_DISP.DELTAMSTEP_FRACTION =  0x21
CM_SSC_DELTAMSTEP_DPLL_DISP.DELTAMSTEP_INTEGER = 0

Let me know if you do indeed see a 10dB reduction with these settings.

Regards,

james