DRA829V: Cortex-R5 MPU implementation

Part Number: DRA829V

Hi,

According to ARM v7R reference manual. Based on implementation the MPU can:

• have a unified memory map
• or separate Instruction and Data memory maps

Please explain which specification does DRA829V R5 implementation follows. The TRM suggest:

• 16 region memory protection unit (MPU)

Does that mean it is a unified memory map?

thanks,
Rizwan