Question about C6747 (OMAP-L137) EDMA3 triggering CPU interrupt.

Hi

Sorry for the late response/missing this post

jun yang said:

2. According to the default EDMA event assignment, EDMA event 0 and 1 are assigned to McASP0, EDMA channel 0 and 1 are used for serving McASP0. Ping-Pong buffers were set for both receiving and transmitting channels. TCC interrupt is enabled. Linking are properly set. Registers of EMR, QEMR, CCERR, ER,  SER, IPR, QEER and QSER are cleared at EDMA3 initilization; and EER was set as 0x03 to enable EDMA event 0 and 1; IER was set as 0x18 to enable TCC interrupt because the TCCs are set as 3 & 4. (Note: All above registers are EDMA3CC registers, not Shadow Region n Channel Registers). It looks working fine because the IPR register was set to 0x18 by the TCC interrupts. However, CPU interrupt didn't happen. CPU IFR keeps as 0.

 

I believe the only thing that you are missing is setting up the DRAE1 to 0x18 (similar to your IER value) to enable EDMA3_CC0_INT1 to traverse to DSP INT controller

jun yang said:

4. Because the CPU INT8 event is EDMA3_CC0_INT1 as default, I set EDMA3 DRAE1 as 0x3 to enable EDMA3 event 0 and 1; then set EDMA3 Shadow Region 1 Channel Registers by clearing ER, SE, IPR, QEER and QSER, and set EER to 0x3 to enable EDMA3 event 0 and 1; IER as 0x18 to enable TCC interrupt. However, IER cannot set, it keeps 0 after write 0x18 into IESR. IPR was never changed by TCC interrupt. (Note: here all EDMA3 register are refered as Shadow Region 1 Channel Registers.)
After added this setting change, CPU interrupt was the same as before, IFR keeps as 0.

The DRAE value needs to match your TCC values and should be same as IER values. If you use channel 0 and 1 (for McASP) but for whatever reason chose TCC for these channels as 3 and 4, then you will see IPR 0x18 set, and if IER = 0x18 and DRAE1 = 0x18 set, you should get the EDMA transfer completion interrupt go to the DSP interrupt controller. 

jun yang said:

A. Is it necessary to set (enable) EDMA3 Shadow Region to enable EDMA3 triggering CPU interrupt? or it is enough to just use EDMA3 Channel Control Registers to have CPU interrupt?

For c6747 class device you wll need to setup the EDMA3 Shadow Region register (DRAEs) appropriately to get the interrupt to the DSP interrupt controller as shown in Figure 12 in the EDMA3 user guide

jun yang said:

B. Why IER in EDMA3 Shadow Region n Channel Registers cannot be set?

To operate on Shadow Region memory map, you need to have the DRAE register setup properly. You should typically work either in the global region or shadow region (not mix usage), and as long as the DRAE is setup appropriately to match your TCC values, you should get an interrupt.

jun yang said:

D. I checked the CPU interrupt event has EDMA3_CC0_INT1 assigned to #8, but I didn't find EDMA3_CC0_INT0 assigned to any number; which means EDMA3_CC0_INT0 cannot trigger CPU interrupt. Why did it designe this way?

The c6747 DSP only device belongs to a family of design that as pin compatible ARM+DSP device (OMAPL137) and ARM only device (AM1707). For devices that incorporate ARM9, the EDMA3_CC0_INT0 is dedicated to go to ARM interrupt controller. So for DSP only device, EDMA3_CC0_INT0 is a don't care and does not exist.

Hope this helps.

Regards

Mukul