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J721E_EVM Ethernet Port handling

jeyaseelan kirubaharan
Expert 1330 points

Hi All ,

We have usercase where we have to route all data packets (MAC and IP packets  ) received in the Ethernet port to the either main2_1 or A72 cores. I see the current ethernet firmware (main2_0 ) has the default PHY configuration for DP83867ERGZT which is used in the EVM board. Have some below questions.

Quad Port Eth expande- EVM board

1. In the EVM, there is a expansion board Quad Port Eth expander which has four RJ45  connecor.

2.Are all connected to single port of mcu cpsw2 ? 

3.Is any of these port is connected to main_cpsw9 ?.

4.Do we need to do  any additional configuration either from ethfw or the client softwares to configure the same. If these four ports are muxed to single port ,how to select the connected one.

PC packet  generator tools

1.We like to have  packet generator tools both for generating raw packets (MAC) and tcp/ip packets. Can you share the link to the insallers where we get the tools installed in Linux.

Custom Eth Interfaces :

1. In our custom board we have 2 more interfaces connected RTL9010(PHY) and Marvel 88Q5050(Ext Switch) connected to CPSW9 ports. For configuring them which files should we have in Ethfw we need to modify.

Can ypu provide answers for the above questions?

With regards,

Jeyaseelan

  • 0
    TI__Genius 14680 points

    Jeyaseelan,

    Quad Port Eth expande- EVM board

    1. Correct. The Quad port expander uses QSGMII to four RJ45 connectors.

    2 & 3. There are four ports on the CPSW9G that are used. These are mapped to a single SerDes on the device to communicate to the PHY over QSGMII. The PHY drives four RJ45s, one per CPSW9G port.

    4. Ethernet Firmware in 7.0 is built by default with QSGMII support disabled. Two flavors of CPSW apputils are currently build:
    - cpsw_apputils – excludes QSGMII/I2C support
    - cpsw_apputils_full –includes QSGMII/I2C support

    EthFw is currently linked against cpsw_apputils, so a makefile has to be modified to link against cpsw_apputils_full and the EthFw’s ENABLE_QSGMII_PORTS flag still has to be explicitly defined in the BIOS app


    PC packet generator tools
    1. You can use iperf3 or netperf

    Custom Eth Interfaces :
    1. PDK Board_Library controls Pinmux and enet_ctrl configuration
    PDK cpsw_lld controls the PHY configuration and MAC port configuration (type of interface, speed, duplex, etc..) EthFW configure MAC port usage configuration (which ports of cpsw9g are owned by ethfw)

    Best regards,

    Dave

  • 0 in reply to Dave Bell
    Expert 1330 points

    Hi Dave,

    Thanks for the reply.

    Regarding point 2 , expect some clarification. According to the EVM schematics what we have , there are four RJ45 connectors (assume it is quad pro expander) connected to DP83867ERGZT  PHY which looks connected with RGMII interface (MCU_RGMII1_TDX,MCU_RGMII1_RDX) to MCU_CPSW2G switch, which looks different to the statement in your reply.Can you clarify on the same?

    If in this board only CPSW2 board is used, do i still need to use Eth_firmware for PHY & Switch configuration or can be done through mcu1_0 firmware.

    Please find the snapshot of the schematics for referance.

    With regards,

    Jeyaseelan

  • 0 in reply to jeyaseelan kirubaharan
    TI__Genius 14680 points

    Jeyaseelan,

    The RGMII interface has four differential data lines per direction, but is a single interface and uses a single PHY.

    Separately from the MCU_CPSW2G_RGMII on the main processor board there is a SerDes connector and QSGMII daughterboard with four Ethernet PHYs. This latter set is what I described in my earlier reply. There are additionally four RGMII connections if you have the additional GESI application board.

    For the MCU_CPSW2G_RGMII, you do not need to use the Ethernet Firmware on the R5F. This is required for using the CPSW9G switch only. The CPSW2G can be owned either by the Linux (or HLOS) application on the A72s or by an RTOS application on one of the R5F cores. Please refer to http://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/psdk_rtos_auto/docs/user_guide/developer_notes_ethfw.html#developing-ethernet-based-applications-with-linux-rtos  for guidance.

    Best regards,

    Dave

  • 0 in reply to Dave Bell
    Expert 1330 points

    Hi Dave ,

    Thanks for the reply .Have few more other questions related to the above post.Currently we are using  psdk version 6.02.

    1.Does this version of psdk have SGMII enabled for the CPSG2/9 ports using cpsw app utilities under pdk?

    PDK

    2.Also under i see pdk/packages/drv/cpsw folder ,2 examples are given ,one is the "cpsw_loopback_test" and another "cpsw_nimu_example".Should these examples  be running with CPSW2 interface only and any client cores where this app runs  can access this interface without ipc? 

    3.Is it possible to modify "cpsw_loopback_test" to receive L2 - MAC packets from external port ,instead of just loop back and similarly "cpsw_nimu_example" can be customized for L3-IPv4 with TCP packets?

    4.Does the data path is always through udma for both cpsw2 and cpsw9?

    EthFw

    4. Under  EthFw ,i see there are 2 sample apps provided , app_remoteswitchcfg_server and client.Is the client application/module a must to be used from any other R5F cores,if  EthFw runs the provided server application . Any other demo application like CAN_Eth gateway  in client cores(mcu2_1, mcu3_x) is compatible to switch server app running in mcu2_0 ?

    5. What is virtual MAC ? As per the doc , the host port of cpsw9 is connected with mcu2_0 which will have a MAC.i assume this is a real MAC .Other client cores also provided MAC which are virtual .Is that right?

    MPU1_0(Linux)

    1. s there sample user space applications available from linux side , for  indirectly using/ configuring cpsw9 through Ethfw 

    2.Sample application from linux with tcp/ip stack which directly configuring CPSW2 and consume the data packets

    Your reply for the above would be really useful in starting our ethernet related activities.Kindly share your input on the same.

    With regards,

    Jeyaseelan 

  • 0 in reply to jeyaseelan kirubaharan
    Expert 1330 points

    Hi Dave,

    Sorry for the confusion .I could see one RGMII is connected with MCU CPSW2 port with one 1 RJ45 and another serdes is going to the Quad pro broad connector. As per your display it is going to Quad PHY  with SGMII.

    MCU cpsw5

    I am running the loopback test example under pdk on cpsw2 on mcu1_0 core and could see packets are getting transmitted and received successfully .But when i connected PC tools like iperf3 or packEth , though packets are sent out through PC ethernet to destination board , these packets are not received at the board. i have disabled both PHY & MAC loopback in the example. Does it require any other changes in the s/w to send /receive from external nodes.

    CPSW9:

    Since only single serdes is connected to the Quad port having four PHYs , does all this PHYs connected to single MAC port of the cpsw9. Does each of the PHYs requires require a separate Serdes to connect to each of the four ports of cpsw9.

    Kindly answer for the above querries. Let me know if i still miss something

    With regards,

    Jeyaseelan 

     

  • 0 in reply to jeyaseelan kirubaharan
    Expert 1330 points

    Since  my initial question was clarified , i am making this issue resolved. Still have few follow up questions on the same in the previous two posts. Please clarify them or let me know if i have to open another thread for them.

    With regards,

    Jeyaseelan

  • 0 in reply to jeyaseelan kirubaharan
    TI__Genius 14680 points

    Jeyaseelan,

    Please see replies to your queries below. As this thread is marked resolved, please do create a new post if any of the following do not fully address your questions, or if you have new ones.


    Q1. SDK 6.2 does not have an SGMII example included. Please see e2e.ti.com/.../900935
    Support is included in SDK7.0.

    PDK
    Q2. The PDK loopback test and NIMU example are to be run with the CPSW2G

    Q3. The loopback and NIMU tests can be modified. For supporting TCP we would recommend usign the NDK - software-dl.ti.com/.../02_overview.html

    Q4.Yes, the datapath is through the UDMA

    EthFw
    Q4. Yes, the server application is the EthFw, which owns control of the switch and the remote client can communicate with the server over IPC for control and directly with the switch for data. See software-dl.ti.com/.../sdk_components.html

    Q5. Linux (or HLOS) on the A72 has a virtual MAC driver that will communicate with the EthFw. See - software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/latest/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/J7_CPSW9g_virt_mac.html

    MPU1_0(Linux)
    Q1. CPSW9G support: software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/latest/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/J7_CPSW9g_virt_mac.html

    Q2. CPSW2G support: software-dl.ti.com/.../K3_CPSW2g.html

    MCU cpsw5
    First issue a ping from the SoC. There is a known issue in SDK6.2.


    CPSW9:
    QSGMII uses a shared single SerDes to communicate for 4 separate interfaces. The CPSW9G internally uses (up to) four of its ports and the external PHY has four independent RJ45 connections.

    Best regards,

    Dave