Hi, I´m currently developing an application on a C6424 without BIOS. It involves commanding McBSP transfers (in SPI mode) through EDMA3, and I needed an ISR to be executed for each transfer completion.
Having coded before to understand how EDMA3, interrupts in general (i.e. using timers, GPIO´s, etc) and McBSP work , I had was having trouble to trigger an interrupt by transfer completion with the above design (EDMA3+McBSP0). In other words, McBSP would transfer perfectly, but my ISR wasn´t being called. After scanning the pertinent documentation (spruem5a.pdf - "TMS320C642x DSP Enhanced Direct Memory Access (EDMA3) Controller User's Guide") and fiddling with the code, I came to the conclusion that on spruem5a.pdf , table 4-51 (page 124) each bit is NOT related to a channel, but to a TCC (transfer completion code, as assigned on the OPT register for each PaRAM). Got substantial evidence for this documentation error when I used a random TCC on channel 2 --such as, let´s say, 20-- and my ISR would be executed only when I set DMAIER = (1 << 20), and NOT when using DMAIER = (1 << 2) (for channel 2) before un-reseting the McBSP device (enabling the transfer). P.S.: the target board was fully reset/disconnected/power cycled before each test.
So, please check this issue and correct spruem5a.pdf, or give a hint to whatever I could have missed. Thanks.