Part Number: PROCESSOR-SDK-DRA8X-TDA4X
Other Parts Discussed in Thread: DRA829, TDA4VM
Tool/software: Code Composer Studio
hi~
I have some question with C66X DSP in TDA4 SOC
1. GEL ,i use C:\ti\ccs1010\ccs\ccs_base\emulation\gel\J721E_DRA829_TDA4VM\gel\J721E.gel fro C66x
What is the C66x CPU frequency of this configuration ？？
2. C66x L1P， in the spruil1a.pdf 1.3.3， it mentions “The C66x L1P memory is disabled (not supported) in this device”， but i can use C66_COREPAC_L1P 0x00E00000 as sram
its means L1P can‘t configurable as cache ？
3. C66x L2， in the spruil1a.pdf 1.3.3， “Unified memory controller (UMC) with 288KB L2 memory, only part of which is cacheable”
how many memory can configurable as cache and from witch address?
