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TMS320C6748 SPI slave boot question

David Leung
Prodigy 80 points

Hi All,

I am trying to boot up a C6748 using SPI0 slave mode and I have written the software on the SPI master side following the information in spraat2c.pdf.

It works up to the Start-Word Sychronization (SWS) step.   i.e. After the SPI master sends 0x5853 to the C6748, it can read back 0x5253 from C6748.

However, the next step, Ping Op-code Sychronization (POS), is not working.  After the SPI master sends 0x590B and 0x5853 to C6748, it can only read back 0x0000 and 0x0000 from C6748.

I have the following questions:

(1) I am currently setting up the SPI Master to transmit data on the falling edge of the SPI clock and receive data on the rising edge of the SPI clock.   Is it correct?

(2) Is there any need to have a time delay between the two 16-bit words (0x590B and 0x5853) in the POS?

(3) Is there need to have a time delay between SWS and POS?    Is there any timeout in the bootup code in the Internal ROM?

Any help will be appreciated.

David

 

 

 

 

 

 

  • 0
    Prodigy 80 points

    My implementation currently has a time delay of about 7 milliseconds between the end of SWS and the beginning of POS.  Does the bootup code in the Internal ROM allow a time delay of this duration between SWS and POS?

    Thanks

    David

     

  • 0
    Prodigy 80 points

    Hi All,

    After more investigation and testing, we have found the followings about the SPI slave boot mode:

    (1) We are using the correct clock edges for the SPI master to transmit and receive data, i.e. Falling edge for transmit, rising edge for receive.

    (2) The SPI master has to insert a short time delay between each 16-bit word.   The AIS boot will fail if the time delay is not added.

    (3) There is no time out between SWS and POS.

    Can someone from Texas Instrument tell me the followings:

    (1) What is the minimum time delay needed between each 16-word?   We cannot determine it with our current setup but would like to know about it so that we can reduce the boot up time in the future with a new setup.

    (2) What is the maximum SPI clock frequency that we can use to do the boot up in the SPI slave mode?   With our current setup, we find that we can do it at 7.5 MHz but it won't work at 10 MHz.   We cannot test it at frequency between 7.5 MHz and 10 MHz as it is not supported by our current setup.

    Any help will be appreciated.

    David

     

     

  • 0 in reply to David Leung
    TI__Expert 7290 points

    Hi David,

     

    My sincere apologies for the delayed response.

    David Leung said:
    (1) What is the minimum time delay needed between each 16-word?   We cannot determine it with our current setup but would like to know about it so that we can reduce the boot up time in the future with a new setup.

     

    Can you please check with the wdelay configured in the Master as well as in the slave?

     The Wdelay is the delay between the transmission, this signifies the idle time period at the end of the current transmission. This could be causing the problem. Refer section 2.5.1.3 of http://focus.ti.com/lit/ug/sprufm4h/sprufm4h.pdf

     

     

    David Leung said:

    (2) What is the maximum SPI clock frequency that we can use to do the boot up in the SPI slave mode?   With our current setup, we find that we can do it at 7.5 MHz but it won't work at 10 MHz.   We cannot test it at frequency between 7.5 MHz and 10 MHz as it is not supported by our current setup.

    Any help will be appreciated.

     There are two test setups which we have done during our testing,

    1.       Running the sample application, which configures the SPI in master mode and communicates with the slave (spi flash). Depending on the slave device (SPI flash) requirement , the frequency will be provided by the SPI master to the spi slave. This setup has been verified for the frequency range of 1,5, 15, 20 MHz. It proves that the SPI master can be configured for various frequencies and it works fine.

    2.       In this case, one of the C6748 EVM acts as a slave and other one acts as a Master and the clock provided by the Master to the Slave is 20 MHz and it works fine.

     

    Please let me know if you need any other help.

    Thanks and Regards,

    Sandeep K

  • 0 in reply to Sandeep Krishnaswamy
    Prodigy 80 points

    Hi Sandeep,

    I would like to clarify that we would like to boot up the C6748 using the SPI slave boot mode.    Thus, we have to find out any limitation in the SPI clock frequency and any time delay needed between 16-bit word transmit or receive so that we can set up our SPI master (implemented in a FPGA) in a reliable and efficient manner.

    I have also tried to find out the above using two C6748 EVM (one acting as the SPI master, the other to be boot up in SPI slave mode) and so far I have found out the following limitations:

    (a) During initial stage of boot up (before the PLL is configured), the SPI clock frequency can be up to 3 MHz and there should be at least 29 microseconds between 16-bit read or 16-bit write.    

    (b) During the latter stage of boot up (after the PLL is configured), the SPI clock frequency can be increased to 11.538 MHz and the time delay can be reduced to a minimum of 2.3 microseconds between 16-bit read or 16-bit write.

    Does the above findings make sense to you?   We cannot tell as we don't have access to the source code of the bootloader in the internal ROM.   The version of the internal ROM in our C6748 EVM is d800k002.

    Thanks

    David

     

     

  • 0 in reply to David Leung
    TI__Expert 7290 points

    David,

    It looks like this question is specific to the SOC and the SPI IP you are using.

    The guys from the C67xx forum can answer your question efficiently, so you can post the query at the forum mentioned below,

    http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115.aspx

    Thanks and Regards,

    Sandeep K

  • 0 in reply to Sandeep Krishnaswamy
    Prodigy 80 points

    Hi Sandeep,

    I will do post my question in the other forum.  

    Thanks for your help.

    David

  • 0 in reply to David Leung
    TI__Mastermind 22391 points

    Sandeep

    can you send me the configuration for the testing that you mentioned please. I like to get both the master and the slave. Also wodnering if other speeds was tested or not.

    Thanks

    Regards

    Mohsen