I have a customer asking the following questions:
I have another question and it’s in regard to the relationship between SYSCLK and FSYNC CLK on the C6474. In the TMS320C6474 Hardware Design Guide, SPRAAW7B, sheet 31 it states that:
For proper operation of the AIF, the SYSCLKP/N (which is the antenna interface SERDES reference
clock) and the frame sync clock (either FSYNCCLKP/N or ALTFSYNCCLK) must be generated from the
same clock source and must be assured not to drift relative to each other.
Since there is not a quantitative number given I am not sure if I implemented this correctly. Referring to the attached pdf I initally used a 61.44MHz oscillator and divided it down to get 30.72MHz and buffered it to maintain the 61.44MHz. I used a SY8973L which is low skew and low jitter. I distributed these clocks to my 6 DSPs using LVDS108 repeaters.
It was suggested in my design review by another engineer that I should consider the alternative of placing the SY89873L near the DSP and using the LVDS108 to distribute the 61.44MHz clock.
Is there an advantage/disadvantage to either method?
Does SYSCLK and FSYNCCK have to be matched in length?
