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C6474 memory partition

Yan Li66748
Prodigy 80 points

14.00 Normal 0 false false false EN-US ZH-CN X-NONE I am currently doing a new design with the C6474. Are there any disadvantages to splitting the memory 1.5:1:0.5 versus splitting them evenly 1M:1M:1M? Does the 1.5M memory take a speed penalty because 0.5M may be physically closer to another core?

  • 0
    TI__Guru* 84110 points

    There is no option on the C6474 to use an asymmetric allocation of the 3MB total L2 memory. Only the 1M/1M/1M configuration is supported for this device.

    You would have to refer to other specific TI DSPs to find the timing answer for their L2 distribution. We have asymmetric, shared, local, global, etc. Generally, asymmetric allocation does not hurt access speeds.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 80 points

    I checked the datasheet again and confirmed your statement.  For some reason, the online training: http://learningmedia.ti.com/public/c6474/C64x_Memory_Cache/index.html slide 18 gave conflicting data.

     

    For the 6616 and 6670 that have multicore shared memory, if that memory is configured as L2, will there be a performance hit for the 2048KB shared memory as opposed to the native 1024KB SRAM?

     

    Thanks.

     

    Regards,

    Yan

  • 0 in reply to Yan Li66748
    TI__Guru* 84110 points

    Thank you very much for pointing out this error in the training module. I do not know a specific reason why this feature was removed, but it was most likely to deliver the best possible product for you to use. I will look into an update for this training module.

    Your question on the C6670 is appropriate for the C66x Multicore DSP Forum.

    Regards,
    RandyP