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TMS320C6678：Address remapping in MCSDK

zane xu
Prodigy 200 points
Part Number: TMS320C6678
Other Parts Discussed in Thread: SYSBIOS

IDE: CCS-V9.2

Project: image_processing_openmp_evmc6678l(C:\ti\mcsdk_2_01_02_06\demos\image_processing\openmp\evmc6678l)

The plantform used by this example has the following settings:

I guess, 0x0c200000 is mapped to 0xa0200000 and cache is disabled.

And I did a simple test. When the data at the 0x0c200000 address was modified, the data at 0xa0200000 changed by the same amount.

I think this proves that I was right.

But to my confusion, I did not find the code for address remapping and disabling the cache for that segment of this address.

Can you tell me where this is done?

Looking forward to your reply.

  • 0
    TI__Guru* 95265 points

    Hi,

    You are correct. From C66x corepac user guide:

    4.3.7.2 Special MAR Registers

    3. MAR12 through MAR15 correspond to MSMC memory. These are read-only
    registers, the PC always read as 1. This makes the MSMC memory always
    cacheable within L1D when accessed by its primary address range.

    So, if you use the MSMC address 0x0c00_0000, it is always cached. If you want to make MSMC uncached, you need to use MPAX to map it to another address. Here we map 0x0c02_0000 to 0xa020_0000 with 2MB size. Then you can set the MAR registers for this 0xa020_0000 region to non-cached.

    The MCSDK is obsolete and I don't have it. I have some map file from that,

    0c05bee0 00000120 ti.omp.config.sysbios.ae66 : preinit.oe66 (.text:CSL_XMC_setXMPAXL)
    0c068580 000000c0 ti.omp.config.sysbios.ae66 : preinit.oe66 (.text:initMPAX)
    0c069cc0 000000a0 ti.omp.config.sysbios.ae66 : preinit.oe66 (.text:CSL_XMC_getXMPAXL)
    0c070d40 00000060 ti.omp.config.sysbios.ae66 : preinit.oe66 (.text:CSL_XMC_getXMPAXH)
    0c0742a0 00000040 ti.omp.config.sysbios.ae66 : preinit.oe66 (.text:CSL_XMC_setXMPAXH)
    0c0d871c 00000004 image_processing_openmp_evmc6670l_pe66.oe66 (.const:ti_omp_utils_OpenMP_mpaxIndex__C)
    0c0d8814 00000004 image_processing_openmp_evmc6670l_pe66.oe66 (.const:ti_omp_utils_OpenMP_mpaxRaddr__C)

    I believe the cache and MPAX setup is done inside openMP package. You may set a breakpoint at code like initMPAX or CSL_XMC_setXMPAXL, then you should be able to see how the code is called. 

    Regards, Eric

     

  • 0 in reply to lding
    Prodigy 200 points

    Thank you very much for your reply.

    Can I understand that ti has made processor adaptation and optimization for the standard OpenMP?

    I've implemented address remapping and caching in my code.

    Since I mentioned multicore memory allocation in another question, the reply I got is that I can refer to the implementation of OpenMP.

    I think your answer will solve my question. Can I post a link to this question in another question?

    By the way, I've seen a lot of places where ti no longer provides support for MCSDK, but I didn't see an example of 6678-OpenMP in the latest processor_sdk_rtos, which prefers to be implemented via IPC. Can you help me with that?