I am using the OMAP-L138 SPI interface to communicate with an external chip. The external chip clocks out a status word at the same time the OMAP is sending a data byte to the external chip. However, there is some sort of fixed 4.667 uSec delay between the end of transmitted byte from the OMAP and the beginning of the subsequent transmitted byte from the OMAP. My code (Logic BSL) waits for the receive data to arrive from the external chip, but from my perspective there should be zero wait time since the external chip is sending a byte to the OMAP as the OMAP is sending a byte to the external chip.
// wait for data to arrive.
while (CHKBIT(spi->SPIBUF, RXEMPTY)) {}
Since I am not toggling CS between bytes, I suspect that the various SPIDELAY values do not apply and should therefore not cause a delay between transmitted bytes.
Here is a capture of the SPI lines. The mysterious gap between the two consecutive bytes is 4.667 uS. I need to reduce this gap. My SCLK is 2MHz. Can anyone shed some light on this?
Thx,
MikeH
