AM6548: OSPI specification

Dear TI processor experts,

For R5 to access the FSS slaves, I understand as follows:

R5 can access the FSS memory regions and the FSS memory mapped registers (by 48-bit addressing via the RAT module).

MCU_ARMSS Master Interfaces:
- Peripheral Access (32-bit VBUSP): MCU_ARMSS0_Px
- Memory Access (64-bit VBUSM read-only): MCU_ARMSS0_DBG_RDx
- Memory Access (64-bit VBUSM write-only): MCU_ARMSS0_DBG_WRx

MCU_FSS0 Slave Interfaces:
- Config Interface: MCU_FSS0_CFG
- Data Interface (FSS0): MCU_FSS0_S0
- Data Interface (FSS1): MCU_FSS0_S1

Is my understanding correct?

Best regards,

Daisuke

Dear TI employees,

Is my understanding correct?

Best regards,

Daisuke

Hi,

I'm not sure why you believe that you need to use 40-bit addresses. The memory mapped OSPI is accessible at address 0x50000000, i.e. you can use it without programming any RAT mapping.

The MCU memory map in the TRM calls it "MCU_FSS0_DAT_REG1".

The table Table 12-5840. FSS Memory Regions calls that "Boot Space (Region 1)" - not sure what the meaning of "boot space" is compared to "external memory space", but using the 0x50000000 address range works for us.

Regards,

Dominic

Hi Dominic-san,

Thank you for your reply.

I don't understand about the FSS memory regions.

What is the difference between "Boot Space" and "External Memory Space"?

Can both "Boot Space" and "External Memory Space" be used to both access and directly execute code from external flash device?

Is "Boot Space" used to place the boot image for SPI/QSPI/OSPI boot?

Can "External Memory Space" be used for external flash devices larger than 1Gb (128MB)?

Best regards,

Daisuke

Hello Daisuke-san,

unfortunately I have no idea these regions mean either, but I know that the area at 0x50000000 works to access a 128-Mbit (16 MB) QSPI NOR flash.

At the 0x50000000 region the QSPI is directly accessible at boot time. We're using it in our own SBL, and the "stock" SBL that comes with the processor SDK uses that range to read the SYSFW image.

If you look at pdk_jacinto_07_00_00\packages\ti\drv\spi\soc\am65xx\SPI_soc.c you'll see two different regions being used for A53 and R5f, but I'm still not sure what that means:

#if defined (__aarch64__)
        CSL_MCU_FSS0_DAT_REG0_BASE,        /* OSPI data base address */
#else
        CSL_MCU_FSS0_DAT_REG1_BASE,
#endif

The memory mapped access might only work if the board is configured to boot from QSPI NOR, but not if booting from SD card - we've never looked into anything except QSPI boot for our own board.

Regards,

Dominic

Hi Dominic-san,

Thank you for your reply.

Our customer wants to clarify the OSPI specifications before they start developing a board with AM6548. So I would like to wait for an answer from TI employees to my question.

Best regards,

Daisuke

Hi,

I have some questions about the memory mapped direct mode.

Q1. Does the memory mapped direct mode mean that CPU (load/store instructions) and each master peripheral can directly access data on an external flash device via the internal logical address space, similar to accessing a parallel NOR flash on GPMC?

Q2. Does "12.3.2.5.2 Configuring the OSPI Controller for Optimal Use" in TRM describe how to initialize for the memory mapped direct mode?

Q3. For each of chip-selects, can the internal logical address space be assigned to one selected from the FSS memory regions? For example, assign CSn0 to Region 1, CSn1 to Region 0, and CSn2 to Region 3.

Q4. For all chip-selects, can the internal logical address space be assigned to only one selected from the FSS memory regions? For example, assign all chip-selects into Region 1.

Q5. (If Q3 or Q4 is Yes,) how is the FSS memory region assigned?

Q6. (If Q3 or Q4 is No,) what does each of the FSS memory regions correspond to?

Q7. Can both A53 and R5 access all address spaces in all FSS memory regions? For R5, I understand as my first post above.

Q8. Is the memory mapped direct mode enabled by default in SPI/QSPI/OSPI boot?

Q9. Is "Boot Space (Region 1)" used to read the boot image in SPI/QSPI/OSPI boot?

Q10. DMA is not supported for OSPI, does that mean only CPU (load/store instructions) can access the OSPI Memory Regions (the registers spaces and the FSS memory regions)?

Best regards,

Daisuke

Dear TI employees,

Could you answer my questions?

Best regards,

Daisuke

I have answered several of your questions below.  For the other questions, the answers are pending.  I will follow up with answers to those questions soon.

Q1. Does the memory mapped direct mode mean that CPU (load/store instructions) and each master peripheral can directly access data on an external flash device via the internal logical address space, similar to accessing a parallel NOR flash on GPMC?

A1. Yes, that is correct.

Q2. Does "12.3.2.5.2 Configuring the OSPI Controller for Optimal Use" in TRM describe how to initialize for the memory mapped direct mode?

A2. Yes. DAC refers to the memory mapped direct mode.

Q3. For each of chip-selects, can the internal logical address space be assigned to one selected from the FSS memory regions? For example, assign CSn0 to Region 1, CSn1 to Region 0, and CSn2 to Region 3.

Q4. For all chip-selects, can the internal logical address space be assigned to only one selected from the FSS memory regions? For example, assign all chip-selects into Region 1.

Q5. (If Q3 or Q4 is Yes,) how is the FSS memory region assigned?

Q6. (If Q3 or Q4 is No,) what does each of the FSS memory regions correspond to?

Q7. Can both A53 and R5 access all address spaces in all FSS memory regions? For R5, I understand as my first post above.

Q8. Is the memory mapped direct mode enabled by default in SPI/QSPI/OSPI boot?

A8. Yes.

Q9. Is "Boot Space (Region 1)" used to read the boot image in SPI/QSPI/OSPI boot?

A9. Yes.

Q10. DMA is not supported for OSPI, does that mean only CPU (load/store instructions) can access the OSPI Memory Regions (the registers spaces and the FSS memory regions)?

A10. Indirect access is also an option. See TRM section 12.3.2.4.8.3 Indirect Access Queuing.

-Zack

Hi Zack-san,

Thank you for your reply.

Zack Brown said:

Q10. DMA is not supported for OSPI, does that mean only CPU (load/store instructions) can access the OSPI Memory Regions (the registers spaces and the FSS memory regions)?

A10. Indirect access is also an option. See TRM section 12.3.2.4.8.3 Indirect Access Queuing.

Is the answer to Q10 Yes?

I would appreciate if you could answer to other questions.

Best regards,

Daisuke

The answer to number 10 is no.  You have two options:

1) Direct Access Controller (which is using memory mapped addresses to access the data).  This is what I think you mean by CPU load/store instructions.

2) Indirect Access Controller.

For your other questions:

Q3. For each of chip-selects, can the internal logical address space be assigned to one selected from the FSS memory regions? For example, assign CSn0 to Region 1, CSn1 to Region 0, and CSn2 to Region 3.

Not exactly.  Only 4GB of flash memory can be addressed by the OSPI controller in DAC mode.  Region 0 and 3, both 4GB in size, access the same space on the flash device.  When ECC or authentication takes up part of the flash memory, accessing Region 0 will translate the requested address to a flash address, to avoid reading ECC or authentication data.  Region 3 will not translate the address.

Region 1 can be used to directly access any 128-byte flash address directly from the R5, without using the RAT.  However, it is an overlapping subsection of Region 0.

Q4. For all chip-selects, can the internal logical address space be assigned to only one selected from the FSS memory regions? For example, assign all chip-selects into Region 1.

Chip selects are configured by the OSPI controller, not the FSS subsystem.  Any access to Region 0,1, or 3 will be received by the controller as a 32-bit address.  This address is what determines which CS becomes active, based on the following register fields:

OSPI_CONFIG_REG.ENABLE_AHB_DEC ODER_FLD:

If 1, the active CS is determined by the address received by the controller.  CS0 starts at address 0, CS1 starts immediately after CS0 region, CS2 after CS1, and so on.  The sizes of these partitions are determined by the register OSPI_DEV_SIZE_CONFIG_REG.

If 0, the active CS is not determined by the address, but by the OSPI_CONFIG_REG fields below.

OSPI_CONFIG_REG.PERIPH_CS_LINES _FLD:

A 4 bit field that sets the CS lines.  It can either correspond 1-to-1 with the CS lines, or select CS lines through an encoder.

OSPI_CONFIG_REG.PERIPH_SEL_DEC_ FLD:

Uses an encoder to ensure that only one CS is active at any time.  See the TRM for details on the encoder.

Q5. (If Q3 or Q4 is Yes,) how is the FSS memory region assigned?

See above.

Q6. (If Q3 or Q4 is No,) what does each of the FSS memory regions correspond to?

This is answered in Q3.

Q7. Can both A53 and R5 access all address spaces in all FSS memory regions? For R5, I understand as my first post above.

Yes.

Hi Zack-san,

Thank you for your reply.

Daisuke Maeda said:

Q10. DMA is not supported for OSPI, does that mean only CPU (load/store instructions) can access the OSPI Memory Regions (the registers spaces and the FSS memory regions)?

In TRM, DMA is not supported for OSPI, what does that mean?

Does that mean NAVSS (UDMA, DRU, UTC, and PDMA) is not supported for OSPI?

In TRM, PDMA is supported for SPI, is that incorrect?

Zack Brown said:

Not exactly.  Only 4GB of flash memory can be addressed by the OSPI controller in DAC mode.  Region 0 and 3, both 4GB in size, access the same space on the flash device.  When ECC or authentication takes up part of the flash memory, accessing Region 0 will translate the requested address to a flash address, to avoid reading ECC or authentication data.  Region 3 will not translate the address.

In TRM, ECC is supported for QSPI1 and not for QSPI0.

Does Region 0 not translate the address for QSPI0?

Best regards,

Daisuke

In TRM, DMA is not supported for OSPI, what does that mean?

OSPI does not have a dedicated DMA channel.  However, in Direct Access Mode, the external OSPI memory is mapped to internal memory.  So in Direct Access Mode, you can use mem to mem DMA.