OMAP 5912 boot ROM with soft reset

However before actually resetting the cores we must write this data to the beginning of internal RAM starting at address 0x20000000:

When looking at this data in CCS as disassembly it is a vector table with jumps to 0x000001E8 and 0x000001A0 plus some additional data. To get this data originally we halted the processor after the TI boot ROM exits and before our code starts and copied the block above from internal RAM at the 0x20000000 address. My question is why does the boot ROM behave differently on a hard reset vs a soft reset? If I zero out the first few hundred bytes of internal RAM before performing a soft reset we are not able to come back up into our production code and I would imagine that the internal RAM is zero'd out on a cold start. When connecting on CCS after a reset without writing the above data it looks as though the processor was continually looping through the boot ROM code. The only thing I can imagine that is happening is that the boot ROM is doing some check to see whether or not it is coming up out of a software reset or from a cold powerup and in the soft reset case checking that some values are in internal RAM already. The work around to this of course is to write this data on powerup to the beginning of internal RAM so that way if there is an unexpected reset the boot ROM will successfully run and exit launching into our production code, but before doing this I would feel alot more comfortable if there was a good explanation for the observed behavior. If anymore details are needed they can be provided. I appreciate your time and input.