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TDA4VMXEVM: TIDL - Input/output padding strategies

F_Fontana
Prodigy 140 points

Part Number: TDA4VMXEVM

Goodmorning,

I'm a bit confused on the padding strategies used for input and output tensors on a DNN model converted with TIDL.

I have a model that has these input and output tensors: 

- Input Tensor => Shape (NCHW) 1x3x64x192,  Paddings L=1, T=1, R=0, B=2, Ch=0

- Output Tensor 1 => Shape (NCHW) 1x2x64x192,  Paddings L=1, T=1, R=0, B=4, Ch=0

- Output Tensor 2 => Shape (NCHW) 1x4x64x192,  Paddings L=1, T=1, R=0, B=4, Ch=0

What is not so clear to me is why the Bottom padding changes even if the height and width of the feature map is the same and, eventually, it's relationship with the number of channels.

What are the rules for paddings?

Avoiding paddings by changing in/out tensors shapes (where possible) could be useful to optimize execution?

Thanks,

Federico

  • 0
    TI__Mastermind 22145 points

    The padding requirement depends on the parameter used in the intermediate layers as well, as our graph compiler optimizes the padding requirements of each layer.

    Padding requirements also depends on a few other parameters of the memory allocation in the graph compiler.

    This is the main reason we have pad parameters in the IO Buff decsriptor structure.

    FYI - For output buffers, These Padded memory regions need not filled with zeros. this memory placeholder for efficient processing and DMA transfers.