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How do I interrupt on AFSR1 in GPIO mode?

Alex Barry
Intellectual 360 points

I have a design using a C6713B that uses the AFSR1 (HHWIL) pin in GPIO mode.  All of the other McASP1 pins are used in GPIO mode as well. ACLKR1 is used as a control output that rarely changes.

I am trying to figure out if there is a way to generate an interrupt on the rising edge of AFSR1 in this mode.  I've been reading SPRU041, but it is not obvious what I need to set up.  It looks like I need to set bit 3 in AGBLCTL (RSMRST), but that seems to generate RSYNCERR in RSTAT, but not RSTAFRM.  Would it be reasonable to use RSYNCERR (clearing it in ISR) be workable?

  • 0
    TI__Genius 14545 points

    Alex,

     When using McASP pins as GPIOs (GPIO setting in  Register <PFUNC>), the logic levels on the GPIO are controlled by the Register <PDSET> and  Regiseter <PDCLR>.

    The state machines are used when the McASP is configured for audio. McASP setting in Register <PFUNC>.

  • 0 in reply to dabuan
    Intellectual 360 points

    Oops, I should have mentioned that I am using AFSR1 as an input.

  • 0 in reply to Alex Barry
    TI__Genius 14545 points

    Alex,

         You may find figure 2.8 on Page 33 of the C6000 McASP User Guide helpful.

  • 0 in reply to dabuan
    Intellectual 360 points

    All I take away from that diagram is that AFSR will be routed to the PDIN[31] bit.  The current algorithm polls that bit, and that works fine.  I am hoping to figure out a way to use the McASP module to generate an interrupt on the rising edge of the signal, when it is used as a GPIO input and not as a real frame sync.

  • 0 in reply to Alex Barry
    TI__Genius 14545 points

    Alex,

    Alex Barry said:
    I am hoping to figure out a way to use the McASP module to generate an interrupt on the rising edge of the signal, when it is used as a GPIO input and not as a real frame sync.

        You'll need to reference to see if any of the PDIN bits are routed to the DSP interrupt controller on your device. If they are not available, the GPIO's will not be able to be used to trigger an interrupt. It's likely that they will not be available as interrupts, however you may be able to use other GPIO's on the device which cause events that are routed to the CPU Interrupt Controller.

     

  • 0 in reply to dabuan
    Intellectual 360 points

    The board is completed, so I don't have any flexibility to move the signal to a GPIO.  The AFSR1 pin does not route to the GPIO module, and PDIN does not route to any of the interrupts on the 6713.  So, I'm stuck with polling unless I can figure out a way to (ab)use the McASP frame sync interrupt.

  • 0 in reply to Alex Barry
    TI__Genius 14545 points

    Alex,

    Alex Barry said:
    So, I'm stuck with polling unless I can figure out a way to (ab)use the McASP frame sync interrupt.

     

      The Frame Sync interrupt is internally generated by the Frame Sync Generator, which by default are held in reset. I believe the Frame Sync generators run off the ACLKR input clock. You can confirm this with the McASP User Guide.

    So, unless you can -somehow- supply a clock to the ACLKR pin of the device,  that the Frame Sync interrupt will never be generated. 

    This additionally means that the ACLKR pin would need to be configured as a McASP pin in the PFUNC register as well. Not sure if it's used as a GPIO output on your board or not.