Dear experts,
I have a very complex situation I'm unable to solve. Let start describing my setup.
I'm using Linux on the ARM side of a OMAP-L138. I'm working with
linux-2.6.33-rc4-psp03.20.00.13 and gcc version 4.3.3 (Sourcery G++ Lite 2009q1-203).
My goal is read a continuous stream of data from the McAsp and alternatively save them on disk
(sata) or stream them trough Ethernet.
I saw the sound/soc/davinci driver, but in order to have a better control of the data flow
I wrote my own driver. At this stage I have a beta driver that supports EDMA transfer
from and to the McAsp serializers. In order to measure the achievable performance I configure
the McAsp in loopback using 8 serializers in transmission and 8 serializers in reception.
I make use of the AFIFO in both directions. From a user space application I read the
data from the McAsp and then I write them on the disk or on the net.
My system almost works, but sometime I experience a strange situation: EDMA reports miss events.
This happens for both destinations (SATA or ETH) and with several combination of parameters.
Of course this problem happens more often if I run the McAsp at higher data rate. I'm very far from
the performance described in the wiki (always below 1 MB/s, globally).
After reading carefully various thread in the forum my actual setup is:
8 tx / 8 rx serializers
WFIFO level 56
RFIFO level 56
Both AXEVT and AREVT are set to EVENTQ_1
I modified the priority of the EVENTQ_1 in devices-da8xx.c setting as follows,
static const s8 da8xx_queue_priority_mapping[][2] = {
/* {event queue no, Priority} */
{0, 3},
{1, 1},
{-1, -1}
};
but I suppose this has no impact due to the function assign_priority_to_queue in
dma.c uses EDMA_QUEPRI register that is not used in the OMAP-L138 (both the
McAsp guide and the processor guide state that).
My driver sets PBBPR to 0x00000020 (as suggested in the
wiki and in various post in the forum) and MSTPRI1 to 0x44441277, but this not solve
the problem.
Finally, when the test hangs, I got DMAERR in both transmission and reception status
register and EMR0 is 0x00000003, indicating a missed event on both DMA.
My guess is that I'm running in some resource sharing issue having some other master
locking the DDR or the bus for long time, but I have no clues on the source of the
problem. May be disabing interrupt for long time can have some impact too.
Can you see any setting that can explain the actual behavior? or that I am missing?
Can you suggest me a strategy to find out the root of the problem (how debug this kind of
conflicts)?
Any idea or suggestion will be highly appreciated.
Regards,
Alberto