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TDA4VM: MCUSW CAN profile app on MCU1_0 and A72 run Linux not working

Amitkumar Makani
Intellectual 350 points
Part Number: TDA4VM
Other Parts Discussed in Thread: SYSBIOS

Hi,

Please find previous discussion https://e2e.ti.com/support/processors/f/791/p/931472/3461400#3461400 here.

Regards,

-Makani

  • 0
    Intellectual 350 points

    Hi Karan,

    Thank you for update.

    I don't need MAIN domain CAN transceivers so I will disable and give try.

    Basically A72 Linux and mcu1_0 use IPC for data transfer and we want to use mcu1_0 only for CAN activity. 

    Regards,

    -Makani

  • 0 in reply to Amitkumar Makani
    TI__Guru* 77074 points

    Hi Makani,

    Yes, please try that. Right now too you can quickly try by halting at u-boot (press enter at the uboot prompt) - this might work if the issue is with linux.

    You firmware in the above case will be loaded as it is the R5 SPL loading it.

    Regards,

    Karan

  • 0 in reply to Karan Saxena
    Intellectual 350 points

    Hi Karan,

    I have tried halting u-boot, In that case SPL load the MCU FW but it stuck once BIOS_start() call happens.

    Basically can_profile_app demo code there is task function [ CanApp_TaskFxn() ] which is not going to execute. So the issue is even before loading Linux.

    I'm looking .lds (linker_r5_sysbios.lds) and .cfg files of the application demo applications.

    Thanks,

    -Makani

  • 0 in reply to Amitkumar Makani
    Intellectual 350 points

    Hi Karan,

    I'm able to run can_profile_app on mcu1_0 and A72 run Linux.

    Basically there was memory overlap related issues (I have completely modified  linker_r5_sysbios.lds).

    Thanks,

    -Makani

  • 0 in reply to Amitkumar Makani
    TI__Guru* 77074 points

    Hi Makani,

    Thanks for the update!

    Please share the modified linker file - as I remeber from 6.02 time frame that I was able to get the mcu1_0 application running from SPL w/o any change to the memory map.

    Regards,

    Karan

  • 0 in reply to Karan Saxena
    Intellectual 350 points

    Hi Karan,

    I have integrated linker_r5_sysbios.lds file with my working IPC code (it use btcm), So it won't be exactly same for your reference.

    I'm not able to attach with .lds extension so changed to .txt

    Thanks,

    -Makani

    linker_r5f_mcu1_0_btcm_sysbios.txt
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    /*----------------------------------------------------------------------------*/
    /* File: linker_r5f_mcu1_0_btcm_sysbios.lds */
    /* Description: */
    /* Link command file for J7ES MCU1_0 view */
    /* TI ARM Compiler version 15.12.3 LTS or later */
    /* */
    /* (c) Texas Instruments 2018, All rights reserved. */
    /*----------------------------------------------------------------------------*/
    /* History: */
    /* Aug 26th, 2016 Original version .......................... Loc Truong */
    /* Aug 01th, 2017 new TCM mem map .......................... Loc Truong */
    /* Nov 07th, 2017 Changes for R5F Init Code.................. Vivek Dhande */
    /* Sep 17th, 2018 Added DDR sections for IPC................. J. Bergsagel */
    /* Sep 26th, 2018 Extra mem sections for IPC resource table.. J. Bergsagel */
    /* Nov 06th, 2018 Correction to TCM addresses for MCU1_0..... J. Bergsagel */
    /* Nov 07th, 2018 Split up OCMRAM_MCU for split-mode R5Fs.... J. Bergsagel */
    /* Feb 20th, 2019 Use R5F BTCM memory for boot vectors........J. Bergsagel */
    /* Apr 23th, 2019 Changes for R5F startup Code............... Vivek Dhande */
    /*----------------------------------------------------------------------------*/
    /* Linker Settings */
    /* Standard linker options */
    --retain="*(.bootCode)"
    --retain="*(.startupCode)"
    --retain="*(.startupData)"
    --fill_value=0
    --stack_size=0x2000
    --heap_size=0x1000
    -stack 0x2000 /* SOFTWARE STACK SIZE */
    -heap 0x2000 /* HEAP AREA SIZE */
    #define DDR0_ALLOCATED_START 0xA0000000
    #define MCU1_0_EXT_DATA_BASE (DDR0_ALLOCATED_START + 0x00100000)
    #define MCU1_0_R5F_MEM_TEXT_BASE (DDR0_ALLOCATED_START + 0x00200000)
    #define MCU1_0_R5F_MEM_DATA_BASE (DDR0_ALLOCATED_START + 0x00300000)
    #define MCU1_0_DDR_SPACE_BASE (DDR0_ALLOCATED_START + 0x00400000)
    #define MCU1_1_ALLOCATED_START DDR0_ALLOCATED_START + 0x01000000
    #define MCU1_1_EXT_DATA_BASE (MCU1_1_ALLOCATED_START + 0x00100000)
    #define MCU1_1_R5F_MEM_TEXT_BASE (MCU1_1_ALLOCATED_START + 0x00200000)
    #define MCU1_1_R5F_MEM_DATA_BASE (MCU1_1_ALLOCATED_START + 0x00300000)
    #define MCU1_1_DDR_SPACE_BASE (MCU1_1_ALLOCATED_START + 0x00400000)
    #define MCU2_0_ALLOCATED_START DDR0_ALLOCATED_START + 0x02000000
    #define MCU2_0_EXT_DATA_BASE (MCU2_0_ALLOCATED_START + 0x00100000)
    #define MCU2_0_R5F_MEM_TEXT_BASE (MCU2_0_ALLOCATED_START + 0x00200000)
    #define MCU2_0_R5F_MEM_DATA_BASE (MCU2_0_ALLOCATED_START + 0x00300000)
    #define MCU2_0_DDR_SPACE_BASE (MCU2_0_ALLOCATED_START + 0x00400000)
    #define MCU2_1_ALLOCATED_START DDR0_ALLOCATED_START + 0x03000000
    #define MCU2_1_EXT_DATA_BASE (MCU2_1_ALLOCATED_START + 0x00100000)
    #define MCU2_1_R5F_MEM_TEXT_BASE (MCU2_1_ALLOCATED_START + 0x00200000)
    #define MCU2_1_R5F_MEM_DATA_BASE (MCU2_1_ALLOCATED_START + 0x00300000)
    #define MCU2_1_DDR_SPACE_BASE (MCU2_1_ALLOCATED_START + 0x00400000)
    #define ATCM_START 0x00000000
    #define BTCM_START 0x41010000
    -e __VECS_ENTRY_POINT
    --retain="*(.ipcCopyVecsToExc)"
    --define FILL_PATTERN=0xFEAA55EF
    --define FILL_LENGTH=0x100
    /*----------------------------------------------------------------------------*/
    /* Memory Map */
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX