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Hi,
Please find previous discussion https://e2e.ti.com/support/processors/f/791/p/931472/3461400#3461400 here.
Regards,
-Makani
Hi Karan,
Thank you for update.
I don't need MAIN domain CAN transceivers so I will disable and give try.
Basically A72 Linux and mcu1_0 use IPC for data transfer and we want to use mcu1_0 only for CAN activity.
Regards,
-Makani
Hi Makani,
Yes, please try that. Right now too you can quickly try by halting at u-boot (press enter at the uboot prompt) - this might work if the issue is with linux.
You firmware in the above case will be loaded as it is the R5 SPL loading it.
Regards,
Karan
Hi Karan,
I have tried halting u-boot, In that case SPL load the MCU FW but it stuck once BIOS_start() call happens.
Basically can_profile_app demo code there is task function [ CanApp_TaskFxn() ] which is not going to execute. So the issue is even before loading Linux.
I'm looking .lds (linker_r5_sysbios.lds) and .cfg files of the application demo applications.
Thanks,
-Makani
Hi Karan,
I'm able to run can_profile_app on mcu1_0 and A72 run Linux.
Basically there was memory overlap related issues (I have completely modified linker_r5_sysbios.lds).
Thanks,
-Makani
Hi Makani,
Thanks for the update!
Please share the modified linker file - as I remeber from 6.02 time frame that I was able to get the mcu1_0 application running from SPL w/o any change to the memory map.
Regards,
Karan
Hi Karan,
I have integrated linker_r5_sysbios.lds file with my working IPC code (it use btcm), So it won't be exactly same for your reference.
I'm not able to attach with .lds extension so changed to .txt
Thanks,
-Makani
/*----------------------------------------------------------------------------*/
/* File: linker_r5f_mcu1_0_btcm_sysbios.lds */
/* Description: */
/* Link command file for J7ES MCU1_0 view */
/* TI ARM Compiler version 15.12.3 LTS or later */
/* */
/* (c) Texas Instruments 2018, All rights reserved. */
/*----------------------------------------------------------------------------*/
/* History: */
/* Aug 26th, 2016 Original version .......................... Loc Truong */
/* Aug 01th, 2017 new TCM mem map .......................... Loc Truong */
/* Nov 07th, 2017 Changes for R5F Init Code.................. Vivek Dhande */
/* Sep 17th, 2018 Added DDR sections for IPC................. J. Bergsagel */
/* Sep 26th, 2018 Extra mem sections for IPC resource table.. J. Bergsagel */
/* Nov 06th, 2018 Correction to TCM addresses for MCU1_0..... J. Bergsagel */
/* Nov 07th, 2018 Split up OCMRAM_MCU for split-mode R5Fs.... J. Bergsagel */
/* Feb 20th, 2019 Use R5F BTCM memory for boot vectors........J. Bergsagel */
/* Apr 23th, 2019 Changes for R5F startup Code............... Vivek Dhande */
/*----------------------------------------------------------------------------*/
/* Linker Settings */
/* Standard linker options */
--retain="*(.bootCode)"
--retain="*(.startupCode)"
--retain="*(.startupData)"
--fill_value=0
--stack_size=0x2000
--heap_size=0x1000
-stack 0x2000 /* SOFTWARE STACK SIZE */
-heap 0x2000 /* HEAP AREA SIZE */
#define DDR0_ALLOCATED_START 0xA0000000
#define MCU1_0_EXT_DATA_BASE (DDR0_ALLOCATED_START + 0x00100000)
#define MCU1_0_R5F_MEM_TEXT_BASE (DDR0_ALLOCATED_START + 0x00200000)
#define MCU1_0_R5F_MEM_DATA_BASE (DDR0_ALLOCATED_START + 0x00300000)
#define MCU1_0_DDR_SPACE_BASE (DDR0_ALLOCATED_START + 0x00400000)
#define MCU1_1_ALLOCATED_START DDR0_ALLOCATED_START + 0x01000000
#define MCU1_1_EXT_DATA_BASE (MCU1_1_ALLOCATED_START + 0x00100000)
#define MCU1_1_R5F_MEM_TEXT_BASE (MCU1_1_ALLOCATED_START + 0x00200000)
#define MCU1_1_R5F_MEM_DATA_BASE (MCU1_1_ALLOCATED_START + 0x00300000)
#define MCU1_1_DDR_SPACE_BASE (MCU1_1_ALLOCATED_START + 0x00400000)
#define MCU2_0_ALLOCATED_START DDR0_ALLOCATED_START + 0x02000000
#define MCU2_0_EXT_DATA_BASE (MCU2_0_ALLOCATED_START + 0x00100000)
#define MCU2_0_R5F_MEM_TEXT_BASE (MCU2_0_ALLOCATED_START + 0x00200000)
#define MCU2_0_R5F_MEM_DATA_BASE (MCU2_0_ALLOCATED_START + 0x00300000)
#define MCU2_0_DDR_SPACE_BASE (MCU2_0_ALLOCATED_START + 0x00400000)
#define MCU2_1_ALLOCATED_START DDR0_ALLOCATED_START + 0x03000000
#define MCU2_1_EXT_DATA_BASE (MCU2_1_ALLOCATED_START + 0x00100000)
#define MCU2_1_R5F_MEM_TEXT_BASE (MCU2_1_ALLOCATED_START + 0x00200000)
#define MCU2_1_R5F_MEM_DATA_BASE (MCU2_1_ALLOCATED_START + 0x00300000)
#define MCU2_1_DDR_SPACE_BASE (MCU2_1_ALLOCATED_START + 0x00400000)
#define ATCM_START 0x00000000
#define BTCM_START 0x41010000
-e __VECS_ENTRY_POINT
--retain="*(.ipcCopyVecsToExc)"
--define FILL_PATTERN=0xFEAA55EF
--define FILL_LENGTH=0x100
/*----------------------------------------------------------------------------*/
/* Memory Map */
MEMORY
{
/* MCU1_R5F_0 local view */
MCU_ATCM (RWX) : origin=ATCM_START length=0x8000
/* MCU1_R5F0_TCMB0 (RWIX) : origin=BTCM_START length=0x8000 (documented only, to avoid conflict below) */
/* MCU1_R5F_0 SoC view */
MCU1_R5F0_ATCM (RWIX) : origin=0x41000000 length=0x8000
MCU1_R5F0_BTCM_VECS (RWIX) : origin=0x41010000 length=0x0100
MCU1_R5F0_BTCM (RWIX) : origin=0x41010100 length=0x7F00
DDR0_RESERVED (RWIX) : origin=0x80000000 length=0x20000000 /* 512MB */
MCU1_0_IPC_DATA (RWIX) : origin=DDR0_ALLOCATED_START length=0x00100000 /* 1MB */
MCU1_0_EXT_DATA (RWIX) : origin=MCU1_0_EXT_DATA_BASE length=0x00100000 /* 1MB */
MCU1_0_R5F_MEM_TEXT (RWIX) : origin=MCU1_0_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
MCU1_0_R5F_MEM_DATA (RWIX) : origin=MCU1_0_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
MCU1_0_DDR_SPACE (RWIX) : origin=MCU1_0_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
MCU1_1_IPC_DATA (RWIX) : origin=MCU1_1_ALLOCATED_START length=0x00100000 /* 1MB */
MCU1_1_EXT_DATA (RWIX) : origin=MCU1_1_EXT_DATA_BASE length=0x00100000 /* 1MB */
MCU1_1_R5F_MEM_TEXT (RWIX) : origin=MCU1_1_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
MCU1_1_R5F_MEM_DATA (RWIX) : origin=MCU1_1_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
MCU1_1_DDR_SPACE (RWIX) : origin=MCU1_1_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
MCU2_0_IPC_DATA (RWIX) : origin=MCU2_0_ALLOCATED_START length=0x00100000 /* 1MB */
MCU2_0_EXT_DATA (RWIX) : origin=MCU2_0_EXT_DATA_BASE length=0x00100000 /* 1MB */
MCU2_0_R5F_MEM_TEXT (RWIX) : origin=MCU2_0_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
MCU2_0_R5F_MEM_DATA (RWIX) : origin=MCU2_0_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
MCU2_0_DDR_SPACE (RWIX) : origin=MCU2_0_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
MCU2_1_IPC_DATA (RWIX) : origin=MCU2_1_ALLOCATED_START length=0x00100000 /* 1MB */
MCU2_1_EXT_DATA (RWIX) : origin=MCU2_1_EXT_DATA_BASE length=0x00100000 /* 1MB */
MCU2_1_R5F_MEM_TEXT (RWIX) : origin=MCU2_1_R5F_MEM_TEXT_BASE length=0x00100000 /* 1MB */
MCU2_1_R5F_MEM_DATA (RWIX) : origin=MCU2_1_R5F_MEM_DATA_BASE length=0x00100000 /* 1MB */
MCU2_1_DDR_SPACE (RWIX) : origin=MCU2_1_DDR_SPACE_BASE length=0x00C00000 /* 12MB */
SHARED_DDR_SPACE (RWIX) : origin=0xAA000000 length=0x01C00000 /* 28MB */
MCU1_0_MSRAM : origin=0x41C40100 length=0x5C000 - 0x100
} /* end of MEMORY */
/*----------------------------------------------------------------------------*/
/* Section Configuration */
SECTIONS
{
.vecs : {
*(.vecs)
} palign(8) > BTCM_START
.vecs : {
__VECS_ENTRY_POINT = .;
} > MCU1_R5F0_BTCM_VECS
xdc.meta (COPY): { *(xdc.meta) } > MCU1_R5F0_BTCM
.init_text : {
boot.*(.text)
*(.text:ti_sysbios_family_arm_MPU_*)
*(.text:ti_sysbios_family_arm_v7r_Cache_*)
} palign(8) > MCU1_R5F0_BTCM
.text:xdc_runtime_Startup_reset__I : {} palign(8) > MCU1_R5F0_BTCM
.bootCode : {} palign(8) > MCU1_R5F0_BTCM
.startupCode : {} palign(8) > MCU1_R5F0_BTCM
.startupData : {} palign(8) > MCU1_R5F0_BTCM, type = NOINIT
.ipcCopyVecsToExc : {} palign(8) > MCU1_R5F0_BTCM
.text : {} palign(8) > MCU1_0_DDR_SPACE
.const : {} palign(8) > MCU1_0_DDR_SPACE
.cinit : {} palign(8) > MCU1_0_DDR_SPACE
.pinit : {} palign(8) > MCU1_0_DDR_SPACE
.bss : {} align(4) > MCU1_0_DDR_SPACE
.data : {} palign(128) > MCU1_0_DDR_SPACE
.data_buffer: {} palign(128) > MCU1_0_DDR_SPACE
.sysmem : {} > MCU1_0_DDR_SPACE
.stack : {} align(4) > MCU1_0_DDR_SPACE
ipc_data_buffer (NOINIT) : {} palign(128) > MCU1_0_DDR_SPACE
.resource_table : {
__RESOURCE_TABLE = .;
} > MCU1_0_EXT_DATA_BASE
/* Additional sections settings */
McalTextSection : fill=FILL_PATTERN, align=4, load > MCU1_0_MSRAM
{
.=align(4);
__linker_spi_text_start = .;
. += FILL_LENGTH;
*(SPI_TEXT_SECTION)
*(SPI_ISR_TEXT_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_spi_text_end = .;
.=align(4);
__linker_gpt_text_start = .;
. += FILL_LENGTH;
*(GPT_TEXT_SECTION)
*(GPT_ISR_TEXT_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_gpt_text_end = .;
.=align(4);
__linker_dio_text_start = .;
. += FILL_LENGTH;
*(DIO_TEXT_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_dio_text_end = .;
.=align(4);
__linker_eth_text_start = .;
. += FILL_LENGTH;
*(ETH_TEXT_SECTION)
*(ETH_ISR_TEXT_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_eth_text_end = .;
.=align(4);
__linker_ethtrcv_text_start = .;
. += FILL_LENGTH;
*(ETHTRCV_TEXT_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_ethtrcv_text_end = .;
.=align(4);
__linker_can_text_start = .;
. += FILL_LENGTH;
*(CAN_TEXT_SECTION)
*(CAN_ISR_TEXT_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_can_text_end = .;
.=align(4);
__linker_wdg_text_start = .;
. += FILL_LENGTH;
*(WDG_TEXT_SECTION)
*(WDG_ISR_TEXT_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_wdg_text_end = .;
.=align(4);
__linker_pwm_text_start = .;
. += FILL_LENGTH;
*(PWM_TEXT_SECTION)
*(PWM_ISR_TEXT_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_pwm_text_end = .;
__linker_adc_text_start = .;
. += FILL_LENGTH;
*(ADC_TEXT_SECTION)
*(ADC_ISR_TEXT_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_adc_text_end = .;
.=align(4);
__linker_cdd_ipc_text_start = .;
. += FILL_LENGTH;
*(CDD_IPC_TEXT_SECTION)
*(CDD_IPC_ISR_TEXT_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_cdd_ipc_text_end = .;
}
McalConstSection : fill=FILL_PATTERN, align=4, load > MCU1_0_MSRAM
{
.=align(4);
__linker_spi_const_start = .;
. += FILL_LENGTH;
*(SPI_CONST_32_SECTION)
*(SPI_CONFIG_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_spi_const_end = .;
.=align(4);
__linker_gpt_const_start = .;
. += FILL_LENGTH;
*(GPT_CONST_32_SECTION)
*(GPT_CONFIG_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_gpt_const_end = .;
.=align(4);
__linker_dio_const_start = .;
. += FILL_LENGTH;
*(DIO_CONST_32_SECTION)
*(DIO_CONST_UNSPECIFIED_SECTION)
*(DIO_CONFIG_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_dio_const_end = .;
.=align(4);
__linker_can_const_start = .;
. += FILL_LENGTH;
*(CAN_CONST_8_SECTION)
*(CAN_CONST_32_SECTION)
*(CAN_CONFIG_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_can_const_end = .;
.=align(4);
__linker_eth_const_start = .;
. += FILL_LENGTH;
*(ETH_CONST_32_SECTION)
*(ETH_CONFIG_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_eth_const_end = .;
.=align(4);
__linker_ethtrcv_const_start = .;
. += FILL_LENGTH;
*(ETHTRCV_CONST_32_SECTION)
*(ETHTRCV_CONFIG_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_ethtrcv_const_end = .;
.=align(4);
__linker_wdg_const_start = .;
. += FILL_LENGTH;
*(WDG_CONST_32_SECTION)
*(WDG_CONFIG_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_wdg_const_end = .;
.=align(4);
__linker_pwm_const_start = .;
. += FILL_LENGTH;
*(PWM_CONST_32_SECTION)
*(PWM_CONFIG_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_pwm_const_end = .;
.=align(4);
__linker_adc_const_start = .;
. += FILL_LENGTH;
*(ADC_CONST_32_SECTION)
*(ADC_CONFIG_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_adc_const_end = .;
.=align(4);
__linker_cdd_ipc_const_start = .;
. += FILL_LENGTH;
*(CDD_IPC_CONST_32_SECTION)
*(CDD_IPC_CONFIG_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_cdd_ipc_const_end = .;
}
McalInitSection : fill=FILL_PATTERN, align=4, load > MCU1_0_MSRAM
{
.=align(4);
__linker_spi_init_start = .;
. += FILL_LENGTH;
*(SPI_DATA_INIT_UNSPECIFIED_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_spi_init_end = .;
.=align(4);
__linker_gpt_init_start = .;
. += FILL_LENGTH;
*(GPT_DATA_INIT_32_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_gpt_init_end = .;
.=align(4);
__linker_pwm_init_start = .;
. += FILL_LENGTH;
*(PWM_DATA_INIT_32_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_pwm_init_end = .;
.=align(4);
__linker_dio_init_start = .;
. += FILL_LENGTH;
*(DIO_DATA_INIT_32_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_dio_init_end = .;
.=align(4);
__linker_eth_init_start = .;
. += FILL_LENGTH;
*(ETH_DATA_INIT_UNSPECIFIED_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_eth_init_end = .;
.=align(4);
__linker_ethtrcv_init_start = .;
. += FILL_LENGTH;
*(ETHTRCV_DATA_INIT_UNSPECIFIED_SECTION)
*(ETHTRCV_DATA_INIT_32_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_ethtrcv_init_end = .;
.=align(4);
__linker_can_init_start = .;
. += FILL_LENGTH;
*(CAN_DATA_INIT_8_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_can_init_end = .;
.=align(4);
__linker_wdg_init_start = .;
. += FILL_LENGTH;
*(WDG_DATA_INIT_UNSPECIFIED_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_wdg_init_end = .;
.=align(4);
__linker_adc_init_start = .;
. += FILL_LENGTH;
*(ADC_DATA_INIT_UNSPECIFIED_SECTION)
*(ADC_DATA_INIT_32_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_adc_init_end = .;
.=align(4);
__linker_cdd_ipc_init_start = .;
. += FILL_LENGTH;
*(CDD_IPC_DATA_INIT_UNSPECIFIED_SECTION)
*(CDD_IPC_DATA_INIT_32_SECTION)
*(CDD_IPC_DATA_INIT_8_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_cdd_ipc_init_end = .;
}
McalNoInitSection : fill=FILL_PATTERN, align=4, load > MCU1_0_MSRAM, type = NOINIT
{
.=align(4);
__linker_spi_no_init_start = .;
. += FILL_LENGTH;
*(SPI_DATA_NO_INIT_UNSPECIFIED_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_spi_no_init_end = .;
.=align(4);
__linker_gpt_no_init_start = .;
. += FILL_LENGTH;
*(GPT_DATA_NO_INIT_UNSPECIFIED_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_gpt_no_init_end = .;
.=align(4);
__linker_dio_no_init_start = .;
. += FILL_LENGTH;
*(DIO_DATA_NO_INIT_UNSPECIFIED_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_dio_no_init_end = .;
.=align(4);
__linker_eth_no_init_start = .;
. += FILL_LENGTH;
*(ETH_DATA_NO_INIT_UNSPECIFIED_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_eth_no_init_end = .;
.=align(4);
__linker_ethtrcv_no_init_start = .;
. += FILL_LENGTH;
*(ETHTRCV_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(ETHTRCV_DATA_NO_INIT_16_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_ethtrcv_no_init_end = .;
.=align(4);
__linker_can_no_init_start = .;
. += FILL_LENGTH;
*(CAN_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(CAN_DATA_NO_INIT_32_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_can_no_init_end = .;
.=align(4);
__linker_wdg_no_init_start = .;
. += FILL_LENGTH;
*(WDG_DATA_NO_INIT_UNSPECIFIED_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_wdg_no_init_end = .;
.=align(4);
__linker_pwm_no_init_start = .;
. += FILL_LENGTH;
*(PWM_DATA_NO_INIT_UNSPECIFIED_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_pwm_no_init_end = .;
__linker_adc_no_init_start = .;
. += FILL_LENGTH;
*(ADC_DATA_NO_INIT_UNSPECIFIED_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_adc_no_init_end = .;
__linker_cdd_ipc_no_init_start = .;
. += FILL_LENGTH;
*(CDD_IPC_DATA_NO_INIT_UNSPECIFIED_SECTION)
*(CDD_IPC_DATA_NO_INIT_8_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_cdd_ipc_no_init_end = .;
}
/* Example Utility specifics */
VariablesAlignedNoInitSection : align=8, load > MCU1_0_MSRAM, type = NOINIT
{
.=align(8);
__linker_cdd_ipc_no_init_align_8b_start = .;
. += FILL_LENGTH;
*(CDD_IPC_DATA_NO_INIT_8_ALIGN_8B_SECTION)
.=align(8);
. += FILL_LENGTH;
__linker_cdd_ipc_no_init_align_8b_end = .;
}
/* Example Utility specifics */
UtilityNoInitSection : align=4, load > MCU1_0_MSRAM, type = NOINIT
{
.=align(4);
__linker_utility_no_init_start = .;
. += FILL_LENGTH;
*(EG_TEST_RESULT_32_SECTION)
.=align(4);
. += FILL_LENGTH;
__linker_utility_no_init_end = .;
}
SciClientBoardCfgSection : align=128, load > MCU1_0_MSRAM, type = NOINIT
{
.=align(128);
__linker_boardcfg_data_start = .;
. += FILL_LENGTH;
*(.boardcfg_data)
.=align(128);
. += FILL_LENGTH;
__linker_boardcfg_data_end = .;
}
/* This section is used for descs and ring mems. It's best to have
* it in OCMRAM or MSMC3 */
McalUdmaSection : fill=FILL_PATTERN, align=128, load > MCU1_0_MSRAM
{
.=align(128);
__linker_eth_udma_start = .;
. += FILL_LENGTH;
*(ETH_UDMA_SECTION)
.=align(128);
. += FILL_LENGTH;
__linker_eth_udma_end = .;
}
McalTxDataSection : fill=FILL_PATTERN, align=128, load > MCU1_0_MSRAM, type = NOINIT
{
.=align(128);
__linker_eth_tx_data_start = .;
. += FILL_LENGTH;
*(ETH_TX_DATA_SECTION)
.=align(128);
. += FILL_LENGTH;
__linker_eth_tx_data_end = .;
}
McalRxDataSection : fill=FILL_PATTERN, align=128, load > MCU1_0_MSRAM, type = NOINIT
{
.=align(128);
__linker_eth_rx_data_start = .;
. += FILL_LENGTH;
*(ETH_RX_DATA_SECTION)
.=align(128);
. += FILL_LENGTH;
__linker_eth_rx_data_end = .;
}
.tracebuf : {} > MCU1_0_EXT_DATA
} /* end of SECTIONS */
/*----------------------------------------------------------------------------*/
/* Misc linker settings */
/*-------------------------------- END ---------------------------------------*/