Part Number: TMS320C6657
Tool/software: TI C/C++ Compiler
Hi.
I use TMS320C6657 UPP.
Channel A transmits data and channel B receives data.
When receiving the first data through channel B, the interrupt occurs normally and the data is normal.
Afterwards, when UPDQ1,2,3 registers are set, an interrupt occurs immediately.
No signal is input, but an interrupt occurs.
At this time, the value stored in the receive buffer is the first data received.
The receive buffer was initialized before receiving the value.
To solve this problem, the cache size was changed and the Cache_inv() function was used, but it was not resolved.
The following development environment is used, and only one core is used.
- CGT : 8.3.2
- SYS/BIOS : 6.75.2.00
- NDK : 3.60.013
- c665x PDK : 2.0.14
- XDCTools : 3.51.11.18_core
void InituPP(void)
{
upp_config_t config;
//UPCTL
config.UPCTL.value = 0;
config.UPCTL.bits.DPFA = 3;
config.UPCTL.bits.DPFB = 3;
config.UPCTL.bits.DPWA = 0;
config.UPCTL.bits.DPWB = 0;
config.UPCTL.bits.IWA = 0; // 8bit interface
config.UPCTL.bits.IWB = 0; // 8bit interface
config.UPCTL.bits.DRA = 0;
config.UPCTL.bits.DRB = 0;
config.UPCTL.bits.DDRDEMUX = 0;
config.UPCTL.bits.SDRTXIL = 0;
config.UPCTL.bits.MODE = 3; // 0 all recv, 1 all xmit, 2 a recv b xmit, 3 a xmit b recv
config.UPCTL.bits.CHN = 1; // Dual channel mode. Channel both active.
// UPICR
config.UPICR.value=0;
config.UPICR.bits.CLKINVA = 0; // Channel A clock inversion.
config.UPICR.bits.CLKDIVA = 8; // Clock divisor for Channel A.
config.UPICR.bits.WAITA = 0; // Channel A WAIT signal enable
config.UPICR.bits.ENAA = 0; // Channel A ENABLE Signal Enable
config.UPICR.bits.ENAB = 1;
config.UPICR.bits.STARTA = 0;
config.UPICR.bits.STARTB = 1;
config.UPICR.bits.ENAPOLA = 0;
config.UPICR.bits.ENAPOLB = 0;
config.UPICR.bits.STARTPOLA = 0;
config.UPICR.bits.STARTPOLB = 0;
// UPIVR (uPP Interface Idle Value Register (UPIVR))
config.UPIVR.value = 0;
config.UPIVR.bits.VALB = 0x0000;
config.UPIVR.bits.VALA = 0x0000;
// UPTCR (Threshold Configuration Register)
config.UPTCR.value = 0;
// UPDLB
config.UPDLB.value = 0;
// UPIES
config.UPIES.value = 0;
// == uPP Interrupt Set Register(UPIES)
config.UPIES.bits.EOLQ = 0; // Interrupt Enable Set for Channel Q End-of-Line
config.UPIES.bits.EOWQ = 1; // Interrupt Enable Set for Channel Q End-of-Window
config.UPIES.bits.ERRQ = 1; // Interrupt Enable Set for Channel Q Error.
config.UPIES.bits.UORQ = 1; // Interrupt Enable Set for Channel Q Underrun/Overflow condition
config.UPIES.bits.DPEQ = 1; // Interrupt Enable Set for Channel Q Programming Error
config.UPIES.bits.EOLI = 0; // Interrupt Enable Set for Channel I End-of-Line
config.UPIES.bits.EOWI = 1; // Interrupt Enable Set for Channel I End-of-Window
config.UPIES.bits.ERRI = 1; // Interrupt Enable Set for Channel I Error
config.UPIES.bits.UORI = 1; // Interrupt Enable Set for Channel I Underrun/Overflow condition.
config.UPIES.bits.DPEI = 1; // Interrupt Enable Set for Channel I Programming Error
// UPPCR
config.UPPCR.value = 0;
config.UPPCR.bits.EN = 1;
UPP->UPPCR = 0x0;
// reset uPP
SETBIT(UPP->UPPCR, UPP_UPPCR_SWRST);
for (i = 0; i < 300; i++) asm(" nop 4"); //wait 200 clock cycles for reset.
CLRBIT(UPP->UPPCR, UPP_UPPCR_SWRST);
UPP->UPCTL = config.UPCTL.value;
UPP->UPICR = config.UPICR.value;
UPP->UPIVR = config.UPIVR.value;
UPP->UPTCR = config.UPTCR.value;
UPP->UPDLB = config.UPDLB.value;
UPP->UPIES = config.UPIES.value;
UPP->UPPCR = config.UPPCR.value;
}
void uPPIDMACmdTx(uint32_t pUppTxCmdBuff)
{
UPP->UPID0 = pUppTxCmdBuff; // add next DMA receiver
UPP->UPID1 = 0x00010080; // 1 lines 128 bytes per line
UPP->UPID2 = 0x00000000; // no offset between lines
}
void uPPDMARxRsp(uint32_t pUppRxRspBuff)
{
UPP->UPQD0 = pUppRxRspBuff; // add next DMA transfer
UPP->UPQD1 = 0x00010080; // 1 lines 128 bytes per line
UPP->UPQD2 = 0x00000000; // no offset between lines
}
ISR function was implemented by referring to 2.6.4 Sample Interrupt Service Routine.
Please let me know if you have any additional information needed to resolve the issue.
Thank you and regards.
Myeongsu
