• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 97 subscribers
  • Views 390 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TCI6638K2K: Self-refresh mode and SoC reset

Tomasz Bachorski
Prodigy 10 points
Part Number: TCI6638K2K

Hello guys,

I'd like to invoke a reset of the K2K with the self-refresh mode enabled, so the memory content is preserved over the Linux reboot. Based on Keystone II Architecture DDR3 Memory Controller User's Guide document[http://www.ti.com/lit/pdf/SPRUHN7], section 2.8, we know that:

The user must ensure that all memory accesses have been completed, and verify that self-refresh is set in the STATUS register before initiating a reset.

The latter requirement is clear and obvious - one has to check (read) that the self-refresh mode bit is properly set in the STATUS register before initiating a reset. How about the former requirement and how to completely fulfill the memory access completion from within Linux? I believe I checked all available docs from the TI K2K main page, but were not able to find any guides or suggestions how to properly handle and test such requirement.

By reset/SoC reset, I understand a software driven, hard reset via PLL controller, invoked by setting RSTCTRL[16].

First assumption is that user has to take care about DMA controller before initiating a reset. If that's true, how it should be done correctly? Should DMA be disabled before entering a self-refresh mode and enabled when we are out of the self-refresh mode (so in u-boot, as self-refresh mode is disabled in u-boot)? Or should it (DMA) be just reset before the self-refresh mode is entered or before the SoC reset is invoked? (so no enabling in u-boot would be needed).

Second assumption is similar to the first one, but in the context of C66x DSPs. Should DSPs be also powered off/on or reset to make sure that self-refresh mode won't be interrupted during the SoC reset? If yes, what is the proper way of handling that? In case of DMA, reset/power off-on should be achieved via PDCTL/MDCTL (correct me if that's a wrong assumption), but it's not so clear how to deal with DSP, based on the C66x CorePac User's Guide.

If my assumptions above are correct, it would be really great to get a reliable information of how to handle these problems correctly. Also, please let me know of any missing parts in my whole reasoning regarding self-refresh mode on this K2K.

  • 0
    TI__Guru* 83965 points

    Hi Tomasz

    Unfortunately our ability to support queries on K2K is now limited. 

    I think the probable sequence is going to be something like below

    1. Software needs to make all the master traffic to both EMIFs to be  stop, and  then  use PSC/LPSC to keep those masters (whichever masters have LPSC to enable/disable clocks) disable in hardware. For EDMA make sure there are no pending/outstanding transfers ( you can try to rely on the TCSTAT registers)
    2. Ensure all traffic to DDR has been stopped (predominantly relying on #1 and ensuring no cores are initiating access to DDR). Set the EMIF in  SWRD state using  corresponding EMIF_LPSC, this will initiate a clock stop request to the EMIF/DDR controller/ The EMIF will accept the clock stop request DDR is put in self refresh.
    3. After this the master core can apply the SOC warm reset.  It should not need to go into WFI/IDLE because it is an SOC reset.

    My understanding is that if you leverage EMIF LPSC to disable clocks, you will not need the self refresh programming in the EMIF controller.

    There are no LPSC for TPCC and TPTCs as far as i can tell, so you would likely need to look at CCSTAT /TCSTAT registers to ensure there is no pending transfers. 

    Unfortunately beyond the public documentation and collateral, there isn't anything I can offer. Such scenarios of are somewhat application and HLOS dependent, so there is no golden sequence that we have that I can share with you.

    I hope this helps.

    Regards

    Mukul