I have a questions about the maximum clock frequency the MIPI CSI-2 interface on the AM654x eval board can cope with. Can TI confirm the limits of the MIPI CSI-2 clock in to the CAMERARX0 block.
TI had previously suggested that the Sony IMX264 sensor would be a good example of an non MIPI image sensor that could work with the AM654x. This image sensor has a fixed frequency LVDS output clock running at 297Mhz. I am worried this clock is going to be to fast for the AM654x. All I can find in the datasheet is a statement about the port being MIPI CSI-2 compliant and able to handle a date rate of 1.5Gbps. By my calculation that could mean a maximum clock rate of 187.5Mhz assuming 4 channels. Or is it 1.5Gbps per channel? We don’t have a copy of the MIPI CSI-2 spec so can TI confirm the limits of the input LVDS clock in to the CAMERARX0 block.
