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66AK2G12: How to configure the PLL settings ?

Luke Vassallo
Prodigy 180 points
Part Number: 66AK2G12
Other Parts Discussed in Thread: SYSBIOS

Hello,

I have the K2GICE EVM and am tryting to setup the pll settings to clock the dsp. So far I have tried the following and have been unsuccessful in doing so :

1) to change the PLL settings in the code by following the procedure in the Technical Reference Manual. When I made changes to the KICK, BOOTCFG and PLL registers I couldn't see these changes in memory, as I stepped through the code line by line. 

2) To some extent I tried to replicate this procedure in 1) using a .gel file, but I received the following error when attempting to modify the first KICK register :


3) The SYSBIOS configuration (.cfg) file does not support the boot section for this part, so I couldn't do much there either. 

On the processor SDK RTOS webpage there is a document that indicates that there are some tested .gel files available but I can't seem to find these. The link below will take you to the specific section in the RTOS documentation. 

Processor SDK RTOS - ICEK2G EVM Hardware Setup - http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_how_to_guides.html#ak2g02-ice-evm-hardware-setup

My question is two parts:
1) Am I doing something that is obviously wrong ?

2) How can I configure the PLL settings ? (The board is configured with a 24MHz crystal)

Thank you

  • 0
    TI__Guru** 116170 points

    Luke,

    I think some of the images that you were trying to add to your E2E post have not come through. However, let me help you get started.

    The GEL file for K2G ICE and K2G EVM are located in the CCS installation at the following location: (default CCS install is in C:\ti)

    • C:\ti\ccs9xx\ccs\ccs_base\emulation\boards\icek2g\gel (Supports 25 Mhz  for 600 MHz clock setting and 800 Mhz DDR speed)
    • C:\ti\ccs901\ccs\ccs_base\emulation\boards\evmk2g\gel (Supports 24 MHz for 600 Mhz and 1Ghz ARM and DSP clock setting with 800/1066 Mhz DDR speed)

    PLL configuration in C code has been implemented as part of the board library that is part of the Processor SDK RTOS PDK component. Please locate the source code and PLL multipliers and dividers located here.

    • pdk_k2g_1_0_xx\packages\ti\board\src\iceK2G\iceK2G_pll.c
    • pdk_k2g_1_0_xx\packages\ti\board\src\evmK2G\evmK2G_pll.c
    • pdk_k2g_1_0_xx\packages\ti\board\src\evmKeystone\board_pll.c

    We also provide a tool for you to simulate and very the PLL clocks using a tool called clock tree tool:

    https://www.ti.com/tool/CLOCKTREETOOL

    Additionally, a good way to physically verify the clock is to direct different PLL output to OBSCLK pin. The GEL has provision for this so if there is a test point on the OBSCLK then you can connect a scope to ensure the clocking is done correctly

    Regards,

    Rahul 

  • 0 in reply to Rahul Prabhu
    Prodigy 180 points

    Hello Rahul, 

    Thank you very much for the information provided. 

    I wasn't looking inside the ccs folder for the gel files, so that explains why I couldn't find. By following your instructions I managed to set up the board clocking using both the gel files and c code.