Part Number: TMDSEVM6678
Tool/software: Code Composer Studio
hi~
i have C6678 custom board
C6678 (DSP) is connected to FPGA (ARTIX17) with EMIF16 ( CS3)
I can't found an examples and any data of EMIF16 communication between DSP and FPGA.
What kind of setting is needed to communicate with FPGA and emif16?
Also, I am curious about how to read() / write().
The code I tested is as follows, and I am curious if it is correct to access in this way.
static uint32_t fpga_config (void)
{
uint32_t power_domain_num = 0;
uint32_t mdctl_emif16_module_num = 3;
uint32_t mdstat_emif16_module_num = 3;
CSL_PSC_MODSTATE mdstat;
/* Wake up EMIF16 module:
mdstat = CSL_PSC_getModuleState(mdstat_emif16_module_num); */
{
uint32_t loop_cnt = 0;
/* program pdctl and mdctl to enable the module. */
CSL_PSC_enablePowerDomain(power_domain_num);
CSL_PSC_setModuleNextState (mdctl_emif16_module_num, PSC_MODSTATE_ENABLE);
// start the process and wait. but timeout in 1000 loops.
CSL_PSC_startStateTransition(power_domain_num);
while(((CSL_PSC_isStateTransitionDone (power_domain_num)) != 0) && (loop_cnt < 1000)) {
loop_cnt++;
}
mdstat = CSL_PSC_getModuleState(mdstat_emif16_module_num);
/* report result. */
if (mdstat != PSC_MODSTATE_ENABLE) {
platform_errno = PLATFORM_ERRNO_PSCMOD_ENABLE;
return FAIL; /* Could not enable the PSC Module */
}
}
/* Config nand FCR reg. 16 bit FPGA */
/* A1CR : CE1 */
hEmif16Cfg->A1CR = (0 \
| (0 << 31) /* selectStrobe */ \
| (0 << 30) /* extWait (never with NAND) */ \
| (0xf << 26) /* writeSetup 10 ns */ \
| (0x3f << 20) /* writeStrobe 40 ns */ \
| (7 << 17) /* writeHold 10 ns */ \
| (0xf << 13) /* readSetup 10 ns */ \
| (0x3f << 7) /* readStrobe 60 ns */ \
| (7 << 4) /* readHold 10 ns */ \
| (3 << 2) /* turnAround 40 ns */ \
| (1 << 0)); /* asyncSize 16-bit bus */
/* CE1 : CS3 */
/* Set the wait polarity */
hEmif16Cfg->AWCCR = (0x80 /* max extended wait cycle */ \
| (0 << 18) /* CS3 uses WAIT0 */ \
| (0 << 28)); /* WAIT0 polarity low */
hEmif16Cfg->IRR = (1 /* clear async timeout */ \
| (1 << 2)); /* clear wait rise */
return SUCCESS;
}
#define CS3_FPGA_DATA_ADDR ((volatile uint8_t *)0x74000000)
static void fpga_set(uint32_t offset, uint16_t v)
{
volatile uint16_t *p = (volatile uint16_t *)CS3_FPGA_DATA_ADDR;
p[offset] = v;
}
uint16_t fpga_get(uint32_t offset)
{
volatile uint16_t *p = (volatile uint16_t *)CS3_FPGA_DATA_ADDR;
return (p[offset]);
}
